| /u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_cfg.c | 19 .ptr1 = 0xD05612C0ul,
|
| H A D | ddr3_k2g.c | 21 .ptr1 = 0xD05612C0ul,
61 .ptr1 = 0xD05612C0ul,
122 .ptr1 = 0xD05612C0ul,
|
| /u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 19 unsigned int ptr1; member in struct:ddr3_phy_config
|
| /u-boot/net/ |
| H A D | wget.c | 237 uchar *ptr1; local
248 ptr1 = map_sysmem((phys_addr_t)pkt_in_q, len);
249 memcpy(ptr1, pkt, len);
250 unmap_sysmem(ptr1);
318 ptr1 = map_sysmem(
321 err = store_block(ptr1,
325 unmap_sysmem(ptr1);
|
| /u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun50i_h616.c | 413 u32 val1, val2, *ptr1, *ptr2; local
441 ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x898);
444 val1 = readl(&ptr1[i]);
449 ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
452 val1 = readl(&ptr1[i]);
459 ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa98);
462 val1 = readl(&ptr1[i]);
468 ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xabc);
471 val1 = readl(&ptr1[i]);
507 u32 val1, val2, *ptr1, *ptr local
[all...] |
| H A D | dram_sun6i.c | 131 writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
|
| /u-boot/lib/efi/ |
| H A D | efi_stub.c | 275 * @ptr1: Pointer to first data block to add
281 void *ptr1, int size1, void *ptr2, int size2)
290 memcpy(hdr + 1, ptr1, size1);
280 add_entry_addr(struct efi_priv *priv, enum efi_entry_t type, void *ptr1, int size1, void *ptr2, int size2) argument
|
| /u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.h | 132 u32 ptr1; member in struct:stm32mp1_ddrphy_timing
|
| H A D | stm32mp1_ddr_regs.h | 150 u32 ptr1; /* 0x1C R/W PHY Timing 1*/ member in struct:stm32mp1_ddrphy
|
| H A D | stm32mp1_ddr.c | 172 DDRPHY_REG_TIMING(ptr1),
|
| /u-boot/board/imgtec/ci20/ |
| H A D | ci20.c | 298 .ptr1 = 0x02230d40,
342 .ptr1 = 0x02d30d40,
|
| /u-boot/arch/arm/mach-imx/imx8ulp/upower/ |
| H A D | upower_api.c | 112 txmsg.ptrs.ptr1 = 0; /* NULL pointer -> 0 offset */
114 txmsg.ptrs.ptr1 = upwr_ptr2offset(ptrval, UPWR_SG_PWRMGMT, UPWR_PMC_MEM_WORDS * 4,
|
| H A D | upower_api.h | 118 u64 ptr1:UPWR_DUAL_OFFSET_BITS; member in struct:upwr_2pointer_msg::__anon3
|
| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 171 u32 ptr1; /* 0x20 */ member in struct:sunxi_mctl_phy_reg
|
| H A D | dram_sun8i_a83t.h | 84 u32 ptr1; /* 0x48 */ member in struct:sunxi_mctl_ctl_reg
|
| H A D | dram_sun8i_a33.h | 84 u32 ptr1; /* 0x48 */ member in struct:sunxi_mctl_ctl_reg
|
| H A D | dram_sun6i.h | 168 u32 ptr1; /* 0x1c */ member in struct:sunxi_mctl_phy_reg
|
| /u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | sdram.c | 83 writel(ddr_config->ptr1, ddr_phy_regs + DDRP_PTR1);
|
| /u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 26 debug_ddr_cfg("ptr1 0x%08X\n", ptr->ptr1);
310 spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) |
|
| H A D | ddr3.c | 43 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
|
| /u-boot/arch/mips/mach-jz47xx/include/mach/ |
| H A D | jz4780_dram.h | 442 u32 ptr1; /* PHY Timing Register 1 */ member in struct:jz4780_ddr_config
|