| /u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_cfg.c | 18 .ptr0 = 0x42C21590ul,
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| H A D | ddr3_k2g.c | 20 .ptr0 = 0x42C21590ul,
60 .ptr0 = 0x42C21590ul,
121 .ptr0 = 0x42C21590ul,
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| /u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 18 unsigned int ptr0; member in struct:ddr3_phy_config
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| /u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.h | 131 u32 ptr0; member in struct:stm32mp1_ddrphy_timing
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| H A D | stm32mp1_ddr_regs.h | 149 u32 ptr0; /* 0x18 R/W PHY Timing 0*/ member in struct:stm32mp1_ddrphy
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| H A D | stm32mp1_ddr.c | 171 DDRPHY_REG_TIMING(ptr0),
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| /u-boot/board/imgtec/ci20/ |
| H A D | ci20.c | 297 .ptr0 = 0x002000d4,
341 .ptr0 = 0x002000d4,
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| /u-boot/arch/arm/mach-imx/imx8ulp/upower/ |
| H A D | upower_api.c | 106 txmsg.ptrs.ptr0 = 0; /* NULL pointer -> 0 offset */
108 txmsg.ptrs.ptr0 = upwr_ptr2offset(ptrval, UPWR_SG_PWRMGMT,
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| H A D | upower_api.h | 117 u64 ptr0:UPWR_DUAL_OFFSET_BITS; member in struct:upwr_2pointer_msg::__anon3
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 170 u32 ptr0; /* 0x1c */ member in struct:sunxi_mctl_phy_reg
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| H A D | dram_sun8i_a83t.h | 83 u32 ptr0; /* 0x44 */ member in struct:sunxi_mctl_ctl_reg
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| H A D | dram_sun8i_a33.h | 83 u32 ptr0; /* 0x44 */ member in struct:sunxi_mctl_ctl_reg
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| H A D | dram_sun6i.h | 167 u32 ptr0; /* 0x18 */ member in struct:sunxi_mctl_phy_reg
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| /u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | sdram.c | 82 writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0);
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| /u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 25 debug_ddr_cfg("ptr0 0x%08X\n", ptr->ptr0);
308 spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) |
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| H A D | ddr3.c | 42 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
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| /u-boot/arch/mips/mach-jz47xx/include/mach/ |
| H A D | jz4780_dram.h | 441 u32 ptr0; /* PHY Timing Register 0 */ member in struct:jz4780_ddr_config
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| /u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun6i.c | 129 &mctl_phy->ptr0);
|