Searched refs:pll_fdiv_ctl0 (Results 1 - 1 of 1) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mm.c652 u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1; local
658 pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
663 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
668 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
673 pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
702 main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
704 pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
706 post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>

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