Searched refs:phy_con2 (Results 1 - 2 of 2) sorted by relevance
| /u-boot/arch/arm/mach-exynos/ |
| H A D | dmc_init_ddr3.c | 146 writel(val, &phy0_ctrl->phy_con2);
147 writel(val, &phy1_ctrl->phy_con2);
167 writel(val, &phy0_ctrl->phy_con2);
168 writel(val, &phy1_ctrl->phy_con2);
699 writel(val, &phy0_ctrl->phy_con2);
700 writel(val, &phy1_ctrl->phy_con2);
730 setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
731 setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
790 setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
791 setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_E
[all...] |
| /u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | dmc.h | 332 unsigned int phy_con2; member in struct:exynos5_phy_control
379 unsigned int phy_con2; member in struct:exynos5420_phy_control
|
Completed in 85 milliseconds