Searched refs:pass (Results 1 - 18 of 18) sorted by relevance

/u-boot/arch/arm/lib/
H A Dvectors_m.S14 mov r0, sp @ pass auto-saved registers as argument
19 mov r0, sp @ pass auto-saved registers as argument
24 mov r0, sp @ pass auto-saved registers as argument
29 mov r0, sp @ pass auto-saved registers as argument
34 mov r0, sp @ pass auto-saved registers as argument
/u-boot/arch/x86/lib/
H A Dcrt0_ia32_efi.S28 pushl %ebx # pass _DYNAMIC as second argument
29 pushl %eax # pass ldbase as first argument
/u-boot/drivers/net/
H A Dmcfmii.c127 int phyaddr, pass; local
135 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
136 if (pass > 1) {
149 printf("PHY type 0x%x pass %d\n", phytype, pass);
159 printf("PHY @ 0x%x pass %d\n", phyno, pass);
H A Dmpc8xx_fec.c730 int pass; local
735 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
736 if (pass > 1) {
/u-boot/arch/arm/cpu/armv7/
H A Dconfig.mk8 # the default so we must pass in -mno-unaligned-access so that it is aware
/u-boot/boot/
H A Dbootmeth-uclass.c159 int i, upto, pass; local
166 for (pass = 0, upto = 0; pass < 1 + include_global; pass++) {
167 if (pass)
186 if (pass ? is_global : !is_global)
/u-boot/drivers/core/
H A Dlists.c112 int pass; local
117 * always succeed on the first pass.
119 for (pass = 0; pass < 10; pass++) {
/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c413 u32 val, pass, tap, cnt, tap_val, last, first; local
449 pass = val & DDR_BIST_COMP_CNT_MASK;
450 pass ^= DDR_BIST_COMP_CNT(8);
451 if (!pass) {
/u-boot/drivers/ddr/altera/
H A Dsequencer.c1282 * pass
1290 * Test writes, can check for a single bit pass or multiple bit pass.
2135 * Stop searching when the read test doesn't pass AND when
2925 * (check for > 1 because loop will increase d even when pass in
3668 int pass; local
3673 /* Reset pass/fail status shown on afi_cal_success/fail */
3685 pass = mem_calibrate(seq);
3702 return pass;
3707 * @pass
3712 debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) argument
3902 u32 pass; local
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/u-boot/fs/jffs2/
H A Djffs2_1pass.c71 * Clipped out all the non-1pass functions, cleaned up warnings,
1269 int i, pass; local
1272 for (pass = 0; pass < 2; pass++) {
1282 if (pass) {
1306 if (pass) {
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-fpa3.h473 aura_level.s.pass = pass_thresh >> shift;
H A Dcvmx-fpa-defs.h289 u64 pass : 8; member in struct:cvmx_fpa_aurax_cnt_levels::cvmx_fpa_aurax_cnt_levels_s
384 u64 pass : 8; member in struct:cvmx_fpa_aurax_pool_levels::cvmx_fpa_aurax_pool_levels_s
H A Dcvmx-ipd-defs.h1499 * Set the pass-drop marks for qos level.
1506 u64 pass : 32; member in struct:cvmx_ipd_qosx_red_marks::cvmx_ipd_qosx_red_marks_s
1573 * Set the pass-drop marks for qos level.
1591 * Set the pass-drop marks for qos level.
1609 * Set the pass-drop marks for qos level.
1644 * Set the pass-drop marks for qos level.
/u-boot/test/fs/
H A Dfs-test.sh413 # if $? is 0 its a pass, else a fail
417 echo pass - "$1"
447 # For a pass they should match.
/u-boot/drivers/ram/octeon/
H A Docteon3_lmc.c760 * sequence. If you issue MRW sequence to do RCW write (in o78 pass
963 // T88 pass 1, skip 4=DAC
975 // NOTE: these are for pass 2.x
3402 // Make sure 78XX pass 1 has valid RTT_WR settings, because
3404 // 78XX pass 1 supports no RTT_WR extension bits
3411 debug("RTT_WR_%d%d set to 120 for CN78XX pass 1\n",
4381 // for DDR3 and OCTEON3 not O78 pass 1.x, override the DAC setting
4907 * first pass through the delay settings by reading
4910 * results from the second pass through the eight delay
5588 // start a pass i
7019 int pass; local
[all...]
/u-boot/drivers/video/
H A Dstb_truetype.h610 // pass these to stbtt_GetPackedQuad to get back renderable quads.
615 // and pass that result as 'font_size':
888 // the same as stbtt_GetCodepointBitmap, but you pass in storage for the bitmap
1708 // in first pass, we load uninterpreted data into the allocated array
3549 if (!points) return; // during first pass, it's unallocated
3624 int i,n=0,start=0, pass;
3642 for (pass=0; pass < 2; ++pass) {
3644 if (pass
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/u-boot/tools/dtoc/
H A Dtest_fdt119 pass
/u-boot/arch/arm/include/asm/arch-octeontx2/csrs/
H A Dcsrs-cgx.h2325 u64 pass : 1; member in struct:cgxx_cmr_rx_steering0x::cgxx_cmr_rx_steering0x_s
2356 u64 pass : 1; member in struct:cgxx_cmr_rx_steering1x::cgxx_cmr_rx_steering1x_s
2382 u64 pass : 1; member in struct:cgxx_cmr_rx_steering_default0::cgxx_cmr_rx_steering_default0_s
2409 u64 pass : 1; member in struct:cgxx_cmr_rx_steering_default1::cgxx_cmr_rx_steering_default1_s

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