Searched refs:nr (Results 1 - 25 of 54) sorted by relevance

123

/u-boot/arch/nios2/include/asm/bitops/
H A Dnon-atomic.h8 * @nr: the bit to set
15 static inline void __set_bit(int nr, volatile unsigned long *addr) argument
17 unsigned long mask = BIT_MASK(nr);
18 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
25 static inline void __clear_bit(int nr, volatile unsigned long *addr) argument
27 unsigned long mask = BIT_MASK(nr);
28 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
37 * @nr: the bit to change
44 static inline void __change_bit(int nr, volatile unsigned long *addr) argument
46 unsigned long mask = BIT_MASK(nr);
61 __test_and_set_bit(int nr, volatile unsigned long *addr) argument
80 __test_and_clear_bit(int nr, volatile unsigned long *addr) argument
91 __test_and_change_bit(int nr, volatile unsigned long *addr) argument
107 test_bit(int nr, const volatile unsigned long *addr) argument
[all...]
H A Datomic.h52 * @nr: the bit to set
62 * Note that @nr may be almost arbitrarily large; this function is not
65 static inline void set_bit(int nr, volatile unsigned long *addr) argument
67 unsigned long mask = BIT_MASK(nr);
68 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
78 * @nr: Bit to clear
86 static inline void clear_bit(int nr, volatile unsigned long *addr) argument
88 unsigned long mask = BIT_MASK(nr);
89 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
99 * @nr
107 change_bit(int nr, volatile unsigned long *addr) argument
127 test_and_set_bit(int nr, volatile unsigned long *addr) argument
151 test_and_clear_bit(int nr, volatile unsigned long *addr) argument
174 test_and_change_bit(int nr, volatile unsigned long *addr) argument
[all...]
/u-boot/include/asm-generic/
H A Dioctl.h65 #define _IOC(dir,type,nr,size) \
68 ((nr) << _IOC_NRSHIFT) | \
83 #define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
84 #define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
85 #define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
86 #define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHEC
[all...]
/u-boot/arch/sandbox/include/asm/
H A Dbitops.h37 extern void set_bit(int nr, void *addr);
39 extern void clear_bit(int nr, void *addr);
41 extern void change_bit(int nr, void *addr);
43 static inline void __change_bit(int nr, void *addr) argument
45 unsigned long mask = BIT_MASK(nr);
46 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
51 static inline int __test_and_set_bit(int nr, void *addr) argument
53 unsigned long mask = BIT_MASK(nr);
54 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
61 static inline int test_and_set_bit(int nr, voi argument
73 __test_and_clear_bit(int nr, void *addr) argument
83 test_and_clear_bit(int nr, void *addr) argument
97 __test_and_change_bit(int nr, void *addr) argument
113 test_bit(int nr, const void *addr) argument
[all...]
/u-boot/arch/m68k/include/asm/
H A Dbitops.h14 extern void set_bit(int nr, volatile void *addr);
15 extern void clear_bit(int nr, volatile void *addr);
16 extern void change_bit(int nr, volatile void *addr);
17 extern int test_and_clear_bit(int nr, volatile void *addr);
18 extern int test_and_change_bit(int nr, volatile void *addr);
23 static inline int test_bit(int nr, __const__ volatile void *addr) argument
27 return (p[nr >> 5] & (1UL << (nr & 31))) != 0;
30 static inline int test_and_set_bit(int nr, volatile void *vaddr) argument
34 volatile char *p = &((volatile char *)vaddr)[(nr
[all...]
/u-boot/arch/arm/mach-omap2/am33xx/
H A Dddr.c41 static inline u32 get_mr(int nr, u32 cs, u32 mr_addr) argument
46 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
48 mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
58 static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val) argument
61 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
62 writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
65 static void configure_mr(int nr, u32 cs) argument
69 while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
71 set_mr(nr, cs, LPDDR2_MR10, 0x56);
73 set_mr(nr, c
84 config_sdram_emif4d5(const struct emif_regs *regs, int nr) argument
183 config_sdram(const struct emif_regs *regs, int nr) argument
211 set_sdram_timings(const struct emif_regs *regs, int nr) argument
224 ext_phy_settings_swlvl(const struct emif_regs *regs, int nr) argument
264 ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) argument
323 config_ddr_phy(const struct emif_regs *regs, int nr) argument
351 config_cmd_ctrl(const struct cmd_control *cmd, int nr) argument
369 config_ddr_data(const struct ddr_data *data, int nr) argument
[all...]
H A Demif4.c31 static void config_vtp(int nr) argument
33 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
34 &vtpreg[nr]->vtp0ctrlreg);
35 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
36 &vtpreg[nr]->vtp0ctrlreg);
37 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
38 &vtpreg[nr]->vtp0ctrlreg);
41 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
52 const struct emif_regs *regs, int nr)
55 config_vtp(nr);
50 config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) argument
[all...]
/u-boot/arch/riscv/include/asm/
H A Dbitops.h35 static inline void __set_bit(int nr, void *addr) argument
40 a += nr >> 5;
41 mask = 1 << (nr & 0x1f);
47 static inline void __clear_bit(int nr, void *addr) argument
52 a += nr >> 5;
53 mask = 1 << (nr & 0x1f);
59 static inline void __change_bit(int nr, void *addr) argument
64 ADDR += nr >> 5;
65 mask = 1 << (nr & 31);
69 static inline int __test_and_set_bit(int nr, voi argument
81 __test_and_clear_bit(int nr, void *addr) argument
93 __test_and_change_bit(int nr, void *addr) argument
108 test_bit(int nr, const void *addr) argument
[all...]
/u-boot/arch/xtensa/include/asm/
H A Dbitops.h16 static inline int test_bit(int nr, const void *addr) argument
18 return ((unsigned char *)addr)[nr >> 3] & (1u << (nr & 7));
21 static inline int test_and_set_bit(int nr, volatile void *addr) argument
25 unsigned char mask = 1u << (nr & 7);
28 tmp = ((unsigned char *)addr)[nr >> 3];
29 ((unsigned char *)addr)[nr >> 3] |= mask;
/u-boot/arch/x86/include/asm/
H A Dbitops.h31 * @nr: the bit to set
36 * Note that @nr may be almost arbitrarily large; this function is not
39 static __inline__ void set_bit(int nr, volatile void * addr) argument
44 :"Ir" (nr));
49 * @nr: the bit to set
56 static __inline__ void __set_bit(int nr, volatile void * addr) argument
61 :"Ir" (nr));
68 * @nr: Bit to clear
76 static __inline__ void clear_bit(int nr, volatile void * addr) argument
81 :"Ir" (nr));
95 __change_bit(int nr, volatile void * addr) argument
112 change_bit(int nr, volatile void * addr) argument
128 test_and_set_bit(int nr, volatile void * addr) argument
148 __test_and_set_bit(int nr, volatile void * addr) argument
167 test_and_clear_bit(int nr, volatile void * addr) argument
187 __test_and_clear_bit(int nr, volatile void * addr) argument
199 __test_and_change_bit(int nr, volatile void * addr) argument
218 test_and_change_bit(int nr, volatile void * addr) argument
238 constant_test_bit(int nr, const volatile void * addr) argument
243 variable_test_bit(int nr, volatile void * addr) argument
[all...]
/u-boot/arch/microblaze/include/asm/
H A Dbitops.h36 static inline void set_bit(int nr, volatile void *addr) argument
42 a += nr >> 5;
43 mask = 1 << (nr & 0x1f);
49 static inline void __set_bit(int nr, volatile void *addr) argument
54 a += nr >> 5;
55 mask = 1 << (nr & 0x1f);
66 static inline void clear_bit(int nr, volatile void *addr) argument
72 a += nr >> 5;
73 mask = 1 << (nr & 0x1f);
79 #define __clear_bit(nr, add
82 change_bit(int nr, volatile void *addr) argument
95 __change_bit(int nr, volatile void *addr) argument
105 test_and_set_bit(int nr, volatile void *addr) argument
121 __test_and_set_bit(int nr, volatile void *addr) argument
133 test_and_clear_bit(int nr, volatile void *addr) argument
149 __test_and_clear_bit(int nr, volatile void *addr) argument
161 test_and_change_bit(int nr, volatile void *addr) argument
177 __test_and_change_bit(int nr, volatile void *addr) argument
192 __constant_test_bit(int nr, const volatile void *addr) argument
197 __test_bit(int nr, volatile void *addr) argument
261 ext2_set_bit(int nr, volatile void *addr) argument
276 ext2_clear_bit(int nr, volatile void *addr) argument
291 ext2_test_bit(int nr, const volatile void *addr) argument
[all...]
/u-boot/include/
H A Dsh_pfc.h143 #define PORT_DATA_I(nr) \
144 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
146 #define PORT_DATA_I_PD(nr) \
147 PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
148 PORT##nr##_IN, PORT##nr##_IN_PD)
150 #define PORT_DATA_I_PU(nr) \
[all...]
H A Dcpu_func.h18 int cpu_status(u32 nr);
19 int cpu_reset(u32 nr);
20 int cpu_disable(u32 nr);
21 int cpu_release(u32 nr, int argc, char *const argv[]);
/u-boot/arch/mips/include/asm/
H A Dbitops.h56 * @nr: the bit to set
61 * Note that @nr may be almost arbitrarily large; this function is not
65 set_bit(int nr, volatile void *addr) argument
67 unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
76 : "ir" (1UL << (nr & 0x1f)), "m" (*m));
81 * @nr: the bit to set
88 static __inline__ void __set_bit(int nr, volatile void * addr) argument
90 unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
92 *m |= 1UL << (nr & 31);
98 * @nr
107 clear_bit(int nr, volatile void *addr) argument
131 change_bit(int nr, volatile void *addr) argument
154 __change_bit(int nr, volatile void * addr) argument
170 test_and_set_bit(int nr, volatile void *addr) argument
199 __test_and_set_bit(int nr, volatile void * addr) argument
221 test_and_clear_bit(int nr, volatile void *addr) argument
251 __test_and_clear_bit(int nr, volatile void * addr) argument
273 test_and_change_bit(int nr, volatile void *addr) argument
302 __test_and_change_bit(int nr, volatile void * addr) argument
327 set_bit(int nr, volatile void * addr) argument
349 __set_bit(int nr, volatile void * addr) argument
369 clear_bit(int nr, volatile void * addr) argument
391 change_bit(int nr, volatile void * addr) argument
413 __change_bit(int nr, volatile void * addr) argument
428 test_and_set_bit(int nr, volatile void * addr) argument
453 __test_and_set_bit(int nr, volatile void * addr) argument
474 test_and_clear_bit(int nr, volatile void * addr) argument
499 __test_and_clear_bit(int nr, volatile void * addr) argument
520 test_and_change_bit(int nr, volatile void * addr) argument
545 __test_and_change_bit(int nr, volatile void * addr) argument
570 test_bit(int nr, const volatile void *addr) argument
790 ext2_set_bit(int nr, void * addr) argument
804 ext2_clear_bit(int nr, void * addr) argument
818 ext2_test_bit(int nr, const void * addr) argument
[all...]
/u-boot/arch/arm/include/asm/
H A Dbitops.h61 extern void set_bit(int nr, volatile void * addr);
63 extern void clear_bit(int nr, volatile void * addr);
65 extern void change_bit(int nr, volatile void * addr);
67 static inline void __change_bit(int nr, volatile void *addr) argument
69 unsigned long mask = BIT_MASK(nr);
70 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
75 static inline int __test_and_set_bit(int nr, volatile void *addr) argument
77 unsigned long mask = BIT_MASK(nr);
78 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
85 static inline int test_and_set_bit(int nr, volatil argument
97 __test_and_clear_bit(int nr, volatile void *addr) argument
107 test_and_clear_bit(int nr, volatile void * addr) argument
121 __test_and_change_bit(int nr, volatile void *addr) argument
134 test_bit(int nr, const void * addr) argument
[all...]
/u-boot/arch/powerpc/include/asm/
H A Dbitops.h31 static __inline__ void set_bit(int nr, volatile void * addr) argument
34 unsigned long mask = 1 << (nr & 0x1f);
35 unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
48 static __inline__ void clear_bit(int nr, volatile void *addr) argument
51 unsigned long mask = 1 << (nr & 0x1f);
52 unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
65 static __inline__ void change_bit(int nr, volatile void *addr) argument
68 unsigned long mask = 1 << (nr & 0x1f);
69 unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
82 static __inline__ int test_and_set_bit(int nr, volatil argument
101 test_and_clear_bit(int nr, volatile void *addr) argument
120 test_and_change_bit(int nr, volatile void *addr) argument
140 test_bit(int nr, __const__ volatile void *addr) argument
285 ext2_set_bit(int nr, void * addr) argument
298 ext2_clear_bit(int nr, void * addr) argument
312 ext2_test_bit(int nr, __const__ void * addr) argument
[all...]
H A Dmp.h14 int is_core_disabled(int nr);
/u-boot/arch/sh/include/asm/
H A Dbitops.h14 static inline void set_bit(int nr, volatile void * addr) argument
20 a += nr >> 5;
21 mask = 1 << (nr & 0x1f);
32 static inline void clear_bit(int nr, volatile void * addr) argument
38 a += nr >> 5;
39 mask = 1 << (nr & 0x1f);
45 static inline void change_bit(int nr, volatile void * addr) argument
51 a += nr >> 5;
52 mask = 1 << (nr & 0x1f);
58 static inline int test_and_set_bit(int nr, volatil argument
74 test_and_clear_bit(int nr, volatile void * addr) argument
90 test_and_change_bit(int nr, volatile void * addr) argument
[all...]
/u-boot/arch/arm/mach-imx/mx6/
H A Dmp.c33 int cpu_reset(u32 nr) argument
36 src->scr |= cpu_reset_mask[nr];
40 int cpu_status(u32 nr) argument
42 printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
46 int cpu_release(u32 nr, int argc, char *const argv[]) argument
52 switch (nr) {
67 src->scr |= cpu_ctrl_mask[nr];
82 int cpu_disable(u32 nr) argument
85 src->scr &= ~cpu_ctrl_mask[nr];
[all...]
/u-boot/arch/arm/include/asm/xen/
H A Dsystem.h22 static inline int synch_test_and_clear_bit(int nr, volatile void *addr) argument
24 u8 *byte = ((u8 *)addr) + (nr >> 3);
25 u8 bit = 1 << (nr & 7);
34 static inline int synch_test_and_set_bit(int nr, volatile void *base) argument
36 u8 *byte = ((u8 *)base) + (nr >> 3);
37 u8 bit = 1 << (nr & 7);
46 static inline void synch_set_bit(int nr, volatile void *addr) argument
48 synch_test_and_set_bit(nr, addr);
52 static inline void synch_clear_bit(int nr, volatile void *addr) argument
54 synch_test_and_clear_bit(nr, add
59 synch_test_bit(int nr, const void *addr) argument
[all...]
/u-boot/arch/arm/mach-zynqmp/
H A Dmp.c58 int cpu_reset(u32 nr) argument
64 static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) argument
68 if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
77 if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
105 static void set_r5_reset(u32 nr, u8 mode) argument
115 if (nr == ZYNQMP_CORE_RPU0) {
129 static void release_r5_reset(u32 nr, u8 mode) argument
134 if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
138 if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
169 int cpu_disable(u32 nr) argument
182 cpu_status(u32 nr) argument
220 write_tcm_boot_trampoline(u32 nr, u32 boot_addr) argument
265 mark_r5_used(u32 nr, u8 mode) argument
286 cpu_release(u32 nr, int argc, char *const argv[]) argument
[all...]
/u-boot/arch/arm/mach-renesas/include/mach/
H A Dirqs.h7 #define gic_spi(nr) ((nr) + 32)
/u-boot/include/linux/
H A Dbitops.h11 #define BIT(nr) (1UL << (nr))
12 #define BIT_ULL(nr) (1ULL << (nr))
13 #define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
14 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
15 #define BIT_ULL_MASK(nr) (1ULL << ((nr)
207 generic_set_bit(int nr, volatile unsigned long *addr) argument
215 generic_clear_bit(int nr, volatile unsigned long *addr) argument
[all...]
/u-boot/arch/arm/mach-mvebu/include/mach/
H A Defuse.h65 int mvebu_read_efuse(int nr, struct efuse_val *val);
67 int mvebu_write_efuse(int nr, struct efuse_val *val);
69 int mvebu_lock_efuse(int nr);
/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmp.c51 int cpu_reset(u32 nr) argument
54 out_be32(&pic->pir, 1 << nr);
62 int cpu_status(u32 nr) argument
69 if (nr == id) {
72 } else if (is_core_disabled(nr)) {
75 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
88 int cpu_disable(u32 nr) argument
92 setbits_be32(&gur->coredisrl, 1 << nr);
97 int is_core_disabled(int nr) { argument
101 return (coredisrl & (1 << nr));
104 cpu_disable(u32 nr) argument
123 is_core_disabled(int nr) argument
146 cpu_release(u32 nr, int argc, char *const argv[]) argument
[all...]

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