| /u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_cfg.c | 28 .mr0 = 0x00001C70ul,
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| H A D | ddr3_k2g.c | 30 .mr0 = 0x00001430ul,
70 .mr0 = 0x00001830ul,
131 .mr0 = 0x00001430ul,
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| /u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 28 unsigned int mr0; member in struct:ddr3_phy_config
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| /u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 38 .mr0 = 6736,
115 writel(dram_para.mr0, &mctl_phy->mr0);
201 writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
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| H A D | dram_sun8i_a83t.c | 135 writel(MCTL_MR0, &mctl_ctl->mr0);
140 writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);
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| H A D | dram_sun8i_a33.c | 134 writel(MCTL_MR0, &mctl_ctl->mr0);
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| H A D | dram_sun50i_h616.c | 881 u32 val, val2, *ptr, mr0, mr2; local
1020 mr0 = 0x1b50;
1023 mr0 = 0x1f14;
1028 writel(mr0, &mctl_ctl->mrctrl1);
1045 writel(mr0, &mctl_ctl->mrctrl1);
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| H A D | dram_sun6i.c | 123 writel(MCTL_MR0, &mctl_phy->mr0);
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| H A D | dram_sun9i.c | 633 writel(mr[0], &mctl_phy->mr0);
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| /u-boot/drivers/ram/sunxi/ |
| H A D | dram_sun20i_d1.c | 191 u32 mr0; local
224 mr0 = 0x06a3;
228 mr0 = 0x0e73;
269 mr0 = 0x1c70;
282 mr0 = 0x1e14;
357 mr0 = 0;
402 mr0 = 0;
435 mr0 = 0;
445 writel(mr0, 0x3103030);
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 24 u32 mr0; member in struct:dram_para
184 u32 mr0; /* 0x54 mode register 0 */ member in struct:sunxi_mctl_phy_reg
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| H A D | dram_sun9i.h | 111 u32 mr0; /* 0x9c mode register 0 */ member in struct:sunxi_mctl_phy_reg
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| H A D | dram_sun8i_a83t.h | 78 u32 mr0; /* 0x30 */ member in struct:sunxi_mctl_ctl_reg
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| H A D | dram_sun8i_a33.h | 78 u32 mr0; /* 0x30 */ member in struct:sunxi_mctl_ctl_reg
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| H A D | dram_sun6i.h | 177 u32 mr0; /* 0x40 mode register 0 */ member in struct:sunxi_mctl_phy_reg
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| /u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.h | 137 u32 mr0; member in struct:stm32mp1_ddrphy_timing
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| H A D | stm32mp1_ddr_regs.h | 159 u32 mr0; /* 0x40 Mode 0*/ member in struct:stm32mp1_ddrphy
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| H A D | stm32mp1_ddr.c | 177 DDRPHY_REG_TIMING(mr0),
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| /u-boot/board/imgtec/ci20/ |
| H A D | ci20.c | 290 .mr0 = 0x420,
334 .mr0 = 0x420,
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| /u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | sdram.c | 77 writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0);
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| /u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 35 debug_ddr_cfg("mr0 0x%08X\n", ptr->mr0);
347 spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 |
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| H A D | ddr3.c | 55 __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
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| /u-boot/arch/mips/mach-jz47xx/include/mach/ |
| H A D | jz4780_dram.h | 438 u16 mr0; /* Mode Register 0 */ member in struct:jz4780_ddr_config
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