Searched refs:miim (Results 1 - 9 of 9) sorted by relevance

/u-boot/drivers/net/mscc_eswitch/
H A Dmscc_miim.c25 static int mscc_miim_wait_ready(struct mscc_miim_dev *miim) argument
27 return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
33 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; local
37 ret = mscc_miim_wait_ready(miim);
43 miim->regs + MIIM_CMD);
45 ret = mscc_miim_wait_ready(miim);
49 val = readl(miim->regs + MIIM_DATA);
63 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; local
66 ret = mscc_miim_wait_ready(miim);
72 MIIM_CMD_OPR_WRITE, miim
77 mscc_mdiobus_init(struct mscc_miim_dev *miim, int *miim_count, phys_addr_t miim_base, unsigned long miim_size) argument
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H A Dmscc_miim.h19 struct mii_dev *mscc_mdiobus_init(struct mscc_miim_dev *miim, int *miim_count,
H A Dservalt_switch.c137 static struct mscc_miim_dev miim[SERVALT_MIIM_BUS_COUNT]; variable in typeref:struct:mscc_miim_dev
398 if (miim[i].miim_base == base && miim[i].miim_size == size)
399 return miim[i].bus;
437 /* Initialize miim buses */
438 memset(&miim, 0x0, sizeof(struct mscc_miim_dev) *
471 mscc_mdiobus_init(miim, &miim_count, addr_base,
H A Dserval_switch.c166 static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT]; variable in typeref:struct:mscc_miim_dev
465 if (miim[i].miim_base == base && miim[i].miim_size == size)
466 return miim[i].bus;
508 /* Initialize miim buses */
509 memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT);
543 mscc_mdiobus_init(miim, &miim_count, addr_base,
H A Dluton_switch.c197 static struct mscc_miim_dev miim[LUTON_MIIM_BUS_COUNT]; variable in typeref:struct:mscc_miim_dev
570 if (miim[i].miim_base == base && miim[i].miim_size == size)
571 return miim[i].bus;
632 /* Initialize miim buses */
633 memset(&miim, 0x0, sizeof(miim) * LUTON_MIIM_BUS_COUNT);
666 mscc_mdiobus_init(miim, &miim_count, addr_base,
H A Docelot_switch.c167 static struct mscc_miim_dev miim[OCELOT_MIIM_BUS_COUNT]; variable in typeref:struct:mscc_miim_dev
508 if (miim[i].miim_base == base && miim[i].miim_size == size)
509 return miim[i].bus;
555 /* Initialize miim buses */
556 memset(&miim, 0x0, sizeof(struct mscc_miim_dev) *
588 mscc_mdiobus_init(miim, &miim_count, addr_base,
H A Djr2_switch.c283 static struct mscc_miim_dev miim[JR2_MIIM_BUS_COUNT]; variable in typeref:struct:mscc_miim_dev
845 if (miim[i].miim_base == base && miim[i].miim_size == size)
846 return miim[i].bus;
901 /* Initialize miim buses */
902 memset(&miim, 0x0, sizeof(struct mscc_miim_dev) * JR2_MIIM_BUS_COUNT);
936 mscc_mdiobus_init(miim, &miim_count, addr_base,
/u-boot/drivers/net/
H A Dpch_gbe.c345 if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
357 u32 miim; local
362 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
365 writel(miim, &mac_regs->miim);
370 return readl(&mac_regs->miim) & 0xffff;
377 u32 miim; local
382 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
385 writel(miim, &mac_regs->miim);
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H A Dpch_gbe.h258 u32 miim; member in struct:pch_gbe_regs

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