/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | fsl_corenet_serdes.h | 18 int serdes_get_lane_idx(int lane); 19 int serdes_get_bank_by_lane(int lane); 20 int serdes_lane_enabled(int lane); 21 enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
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H A D | fsl_corenet2_serdes.h | 10 int serdes_lane_enabled(int lane);
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H A D | p1010_serdes.c | 58 int lane; local 70 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { 71 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; 83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { 84 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
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H A D | fsl_corenet_serdes.c | 65 unsigned int lpd; /* RCW lane powerdown bit */ 99 int serdes_get_lane_idx(int lane) argument 101 return lanes[lane].idx; 104 int serdes_get_bank_by_lane(int lane) argument 106 return lanes[lane].bank; 109 int serdes_lane_enabled(int lane) argument 114 int bank = lanes[lane].bank; 115 int word = lanes[lane].lpd / 32; 116 int bit = lanes[lane].lpd % 32; 128 return !(srds_lpd_b[bank] & (8 >> (lane 193 int lane; local 205 int lane; local 219 int lane, idx, first, last; local 500 int lane, bank, idx; local 670 unsigned int lane; local [all...] |
H A D | mpc8544_serdes.c | 59 int lane; local 71 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { 72 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; 84 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { 85 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
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H A D | p2020_serdes.c | 47 int lane; local 59 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { 60 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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H A D | p1023_serdes.c | 42 int lane; local 53 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { 54 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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H A D | mpc8548_serdes.c | 39 int lane; local 51 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { 52 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane];
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H A D | c29x_serdes.c | 48 int lane; local 64 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { 65 enum srds_prtcl lane_prtcl = ptr->lanes[lane];
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H A D | p1021_serdes.c | 59 int lane; local 72 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { 73 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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/u-boot/arch/arm/cpu/armv7/ls102xa/ |
H A D | fsl_ls1_serdes.h | 10 int serdes_lane_enabled(int lane);
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H A D | ls102xa_serdes.c | 22 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) argument 24 return serdes_cfg_tbl[cfg][lane];
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H A D | fsl_ls1_serdes.c | 80 int lane; local 89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 90 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
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/u-boot/include/mvebu/ |
H A D | comphy.h | 9 int comphy_rx_training(struct udevice *dev, u32 lane);
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/u-boot/drivers/phy/marvell/ |
H A D | comphy_mux.c | 15 * is valid for specific lane. If the type is not valid, 16 * the function update the struct and set the type of the lane as 23 int lane, opt, valid; local 27 for (lane = 0; lane < comphy_max_lanes; 28 lane++, comphy_map_data++, mux_data++) { 42 debug("lane number %d, had invalid type %d\n", 43 lane, comphy_map_data->type); 44 debug("set lane %d as type %d\n", lane, 56 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data, u32 type, int lane) argument 84 u32 lane, value, offset, mask; local [all...] |
H A D | comphy_core.c | 57 u32 lane; local 59 for (lane = 0; lane < chip_cfg->comphy_lanes_count; 60 lane++, comphy_map_data++) { 62 printf("Comphy-%d: %-13s\n", lane, 65 printf("Comphy-%d: %-13s %-10s\n", lane, 72 int comphy_rx_training(struct udevice *dev, u32 lane) argument 77 return chip_cfg->rx_training(chip_cfg, lane);
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H A D | comphy_a3700.c | 354 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane) argument 364 if (lane == 2) 376 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) argument 396 usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane); 410 | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane); 413 usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane); 417 * from lane configuration 419 usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane); 423 usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane); 426 usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane); 691 comphy_sgmii_phy_init(u32 lane, u32 speed) argument 725 comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) argument 996 comphy_a3700_find_lane(const int nodes[3], int node, int port, int *lane, int *invert) argument 1027 int node, lane, port, speed, invert; local 1123 u32 lane, ret = 0; local [all...] |
H A D | comphy_cp110.c | 87 u32 lane, u32 mode) 93 pregs.regs[2] = lane; 114 u32 lane) 117 u32 type = ptr_chip_cfg->comphy_map_data[lane].type; 122 pr_err("Comphy %d isn't configured to SFI\n", lane); 128 ptr_chip_cfg->comphy_base_addr, lane, 0); 135 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, argument 192 ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, comphy_base_addr, lane, type); 223 ret = comphy_smc(MV_SIP_COMPHY_PLL_LOCK, comphy_base_addr, lane, type); 560 int lane, subnod local 86 comphy_smc(u32 function_id, void __iomem *comphy_base_addr, u32 lane, u32 mode) argument 113 comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, u32 lane) argument 621 u32 comphy_max_count, lane, id, ret = 0; local [all...] |
/u-boot/board/freescale/p2041rdb/ |
H A D | eth.c | 30 * that the mapping must be determined dynamically, or that the lane maps to 84 int lane; local 98 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); 99 if (lane < 0) 101 slot = lane_to_slot[lane]; 116 lane = serdes_get_first_lane(XAUI_FM1); 117 if (lane >= 0) { 119 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); 135 int lane; local 170 lane [all...] |
/u-boot/board/highbank/ |
H A D | ahci.c | 82 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) argument 85 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); 87 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); 90 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); 94 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); 97 static void cphy_tx_attenuation_override(u8 phy, u8 lane) argument 103 shift = ((phy == 5) ? 4 : lane) * 4; 110 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); 112 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); 115 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LAN 124 u8 lane = 0, phy = 0; local 156 u8 lane = 0, phy = 0; local [all...] |
/u-boot/arch/mips/mach-octeon/include/mach/ |
H A D | octeon_qlm.h | 57 * @param lane Lane the apply the tuning parameters 65 void octeon_qlm_tune_per_lane_v3(int node, int qlm, int baud_mhz, int lane, int tx_swing, 85 * Disables DFE for the specified QLM lane(s). 90 * @param lane Lane to configure, or -1 all lanes 94 void octeon_qlm_dfe_disable(int node, int qlm, int lane, int baud_mhz, int mode);
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H A D | cvmx-qlm.h | 98 * @param lane Lane in QLM to get 103 u64 cvmx_qlm_jtag_get(int qlm, int lane, const char *name); 109 * @param lane Lane in QLM to set, or -1 for all lanes 113 void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, u64 value); 129 void __cvmx_qlm_pcie_cfg_rxd_set_tweak(int qlm, int lane); 217 * DML 0 lane 0 == GSER0 lane 0 218 * DML 0 lane 1 == GSER0 lane 1 219 * DML 1 lane [all...] |
/u-boot/arch/arm/include/asm/arch-ls102xa/ |
H A D | fsl_serdes.h | 32 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
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/u-boot/arch/arm/mach-tegra/ |
H A D | xusb-padctl-common.c | 131 const struct tegra_xusb_padctl_lane *lane, 141 for (i = 0; i < lane->num_funcs; i++) 142 if (lane->funcs[i] == func) 155 const struct tegra_xusb_padctl_lane *lane; local 159 lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); 160 if (!lane) { 161 pr_err("no lane for pin %s", group->pins[i]); 165 func = tegra_xusb_padctl_lane_find_function(padctl, lane, 168 pr_err("function %s invalid for lane %s: %d", 169 group->func, lane 130 tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl, const struct tegra_xusb_padctl_lane *lane, const char *name) argument [all...] |
/u-boot/drivers/soc/ti/ |
H A D | keystone_serdes.c | 48 struct serdes_cfg lane[SERDES_LANE_CFG_NUM]; member in struct:cfg_entry 51 /* SERDES PHY lane enable configuration value, indexed by PHY interface */ 90 .lane = { 119 u32 size, u32 lane) 124 ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane), 136 ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i); 162 static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane) argument 165 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), 168 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), 173 struct ks2_serdes *serdes, u32 lane) 118 ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane, u32 size, u32 lane) argument 172 ks2_serdes_lane_enable(u32 base, struct ks2_serdes *serdes, u32 lane) argument [all...] |