Searched refs:gpio_regs (Results 1 - 21 of 21) sorted by relevance

/u-boot/board/imgtec/ci20/
H A Dci20.c32 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; local
35 writel(0x30f00000, gpio_regs + GPIO_PXINTC(4));
36 writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4));
37 writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4));
38 writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4));
39 writel(0x30f00000, gpio_regs + GPIO_PXPENC(4));
47 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; local
51 writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
52 writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
53 writel(0x04030000, gpio_regs
74 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; local
86 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; local
110 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; local
221 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; local
[all...]
/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dgpio.c10 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; local
14 return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin);
19 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; local
23 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
24 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
25 writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port));
30 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; local
34 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port));
35 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port));
36 writel(BIT(pin), gpio_regs
[all...]
/u-boot/arch/arm/include/asm/arch-imxrt/
H A Dgpio.h12 struct gpio_regs { struct
/u-boot/board/netgear/dgnd3700v2/
H A Ddgnd3700v2.c20 void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE); local
23 setbits_be32(gpio_regs + GPIO_MODE_6362_REG,
/u-boot/arch/arm/include/asm/arch-imx8/
H A Dgpio.h11 struct gpio_regs { struct
/u-boot/arch/arm/include/asm/arch-imx8ulp/
H A Dgpio.h9 struct gpio_regs { struct
/u-boot/arch/arm/include/asm/arch-imx9/
H A Dgpio.h9 struct gpio_regs { struct
/u-boot/arch/arm/include/asm/mach-imx/
H A Dgpio.h13 struct gpio_regs { struct
/u-boot/drivers/gpio/
H A Dmxc_gpio.c32 struct gpio_regs *regs;
36 struct gpio_regs *regs;
77 struct gpio_regs *regs;
85 regs = (struct gpio_regs *)gpio_ports[port];
104 struct gpio_regs *regs;
112 regs = (struct gpio_regs *)gpio_ports[port];
127 struct gpio_regs *regs;
135 regs = (struct gpio_regs *)gpio_ports[port];
173 static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
182 static void mxc_gpio_bank_direction(struct gpio_regs *reg
[all...]
H A Dimx_rgpio2p.c31 struct gpio_regs *regs;
36 struct gpio_regs *regs;
39 static int imx_rgpio2p_is_output(struct gpio_regs *regs, int offset)
48 static int imx_rgpio2p_bank_get_direction(struct gpio_regs *regs, int offset)
56 static void imx_rgpio2p_bank_direction(struct gpio_regs *regs, int offset,
73 static void imx_rgpio2p_bank_set_value(struct gpio_regs *regs, int offset,
82 static int imx_rgpio2p_bank_get_value(struct gpio_regs *regs, int offset)
224 plat->regs = (struct gpio_regs *)addr;
257 { 0, (struct gpio_regs *)RGPIO2P_GPIO1_BASE_ADDR },
258 { 1, (struct gpio_regs *)RGPIO2P_GPIO2_BASE_ADD
[all...]
H A Dlpc32xx_gpio.c41 struct gpio_regs *regs;
71 struct gpio_regs *regs = gpio_priv->regs;
113 struct gpio_regs *regs = gpio_priv->regs;
153 struct gpio_regs *regs = gpio_priv->regs;
187 struct gpio_regs *regs = gpio_priv->regs;
235 struct gpio_regs *regs = gpio_priv->regs;
306 gpio_priv->regs = (struct gpio_regs *)GPIO_BASE;
H A Dxilinx_gpio.c19 struct gpio_regs { struct
25 struct gpio_regs *regs;
/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dgpio.h9 struct gpio_regs { struct
/u-boot/board/tplink/wdr4300/
H A Dwdr4300.c21 void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE, local
23 if (!gpio_regs)
27 clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22));
28 writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET);
/u-boot/arch/arm/include/asm/arch-mx27/
H A Dgpio.h12 struct gpio_regs { struct
35 struct gpio_regs port[6];
/u-boot/board/timll/devkit3250/
H A Ddevkit3250_spl.c16 static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dgpio.h13 struct gpio_regs { struct
/u-boot/arch/sh/include/asm/
H A Dcpu_sh7752.h100 struct gpio_regs { struct
193 #define GPIO_BASE ((struct gpio_regs *)0xffec0000)
H A Dcpu_sh7753.h100 struct gpio_regs { struct
193 #define GPIO_BASE ((struct gpio_regs *)0xffec0000)
/u-boot/board/BuR/brppt2/
H A Dboard.c406 struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
/u-boot/board/boundary/nitrogen6x/
H A Dnitrogen6x.c875 struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;

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