Searched refs:divr1 (Results 1 - 2 of 2) sorted by relevance
| /u-boot/drivers/clk/stm32/ |
| H A D | clk-stm32h7.c | 505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; local
530 /* get divm1, divp1, divn1 and divr1 */
542 divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
551 log_debug("divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
552 divm1, divn1, divp1, divq1, divr1);
565 return (vco + rate) / divr1;
|
| /u-boot/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mq.c | 86 u32 divr1, divr2, divf1, divf2, divq, div; local
228 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
245 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
|
Completed in 187 milliseconds