Searched refs:ctrl1 (Results 1 - 11 of 11) sorted by relevance

/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dtimer.h8 /* Each timer has 4 control bits in ctrl1 register.
40 u32 ctrl1; member in struct:ast_timer
/u-boot/drivers/timer/
H A Dast_timer.c42 clrbits_le32(&priv->regs->ctrl1,
45 setbits_le32(&priv->regs->ctrl1,
/u-boot/drivers/power/
H A Dtps6586x.c91 int ctrl1, ctrl2; local
98 ctrl1 = tps6586x_read(SUPPLY_CONTROL1);
100 if (ctrl1 == -1 || ctrl2 == -1)
104 is_v2 = (ctrl1 | ctrl2) & CTRL_SM0_SUPPLY2;
/u-boot/drivers/usb/cdns3/
H A Ddrd.h38 __le32 ctrl1; member in struct:cdns3_otg_regs
58 __le32 ctrl1; member in struct:cdns3_otg_legacy_regs
H A Ddrd.c50 reg = readl(&cdns->otg_v0_regs->ctrl1);
52 writel(reg, &cdns->otg_v0_regs->ctrl1);
/u-boot/arch/arm/include/asm/arch-tegra/
H A Dtegra_i2c.h57 u32 ctrl1; /* 00: DVC_CTRL_REG1 */ member in struct:dvc_ctlr
/u-boot/drivers/video/bridge/
H A Danx6345.c175 u8 ctrl1 = req; local
182 ctrl1 |= ANX9804_AUX_LENGTH(len);
192 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);
/u-boot/drivers/net/
H A Dbcm-sf2-eth-gmac.c46 uint32_t ctrl1; member in struct:__anon297
118 printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
119 descp->ctrl1, descp->ctrl2,
150 printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
151 descp->ctrl1, descp->ctrl2,
189 descp->ctrl1 = ctrl;
240 descp->ctrl1 = ctrl;
356 descp->ctrl1 = flags;
H A Dsunxi_emac.c69 u32 ctrl1; member in struct:sunxi_sramc_regs
514 setbits_le32(&sram->ctrl1, 0x5 << 2);
/u-boot/arch/arm/include/asm/arch-hi6220/
H A Dhi6220_regs_alwayson.h14 u32 ctrl1; member in struct:alwayson_sc_regs
267 /* ctrl1 bit definitions */
H A Dhi6220.h23 u32 ctrl1; /*0x0*/ member in struct:peri_sc_periph_regs

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