Searched refs:cs_enable_reg_val (Results 1 - 3 of 3) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_centralization.c78 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; local
90 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS));
516 cs_enable_reg_val[if_id],
538 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; local
554 cs_enable_reg_val,
H A Dddr3_training_leveling.c44 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; local
66 DUAL_DUNIT_CFG_REG, cs_enable_reg_val,
295 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id],
407 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; /* save current CS value */ local
440 DUAL_DUNIT_CFG_REG, &cs_enable_reg_val[if_id],
747 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id],
808 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; local
841 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS));
1141 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id],
H A Dddr3_training_pbs.c51 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; local
64 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS));
871 DUAL_DUNIT_CFG_REG, cs_enable_reg_val[if_id],

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