Searched refs:cs_count (Results 1 - 7 of 7) sorted by relevance
/u-boot/drivers/ddr/marvell/a38x/ |
H A D | xor.c | 23 u32 reg, ui, cs_count; local 35 for (ui = 0, cs_count = 0; 36 (cs_count < num_of_cs) && (ui < 8); 37 ui++, cs_count++) { 48 cs_count = 0; 49 for (ui = 0, cs_count = 0; 50 (cs_count < num_of_cs) && (ui < 8); 51 ui++, cs_count++) {
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/u-boot/drivers/ddr/marvell/axp/ |
H A D | xor.c | 26 u32 reg, ui, base, cs_count; local 50 cs_count = 0; 72 reg_write(XOR_BASE_ADDR_REG(0, cs_count), base); 75 reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000); 76 cs_count++;
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H A D | ddr3_spd.c | 597 __maybe_unused u32 dimm_cnt, cs_count, dimm; local 906 cs_count = 0; 910 if (dimm_info[dimm_cnt].num_of_module_ranks == cs_count) { 912 cs_count = 0; 914 cs_count++; 930 cs_count = 0; 934 if (dimm_info[dimm_cnt].num_of_module_ranks == cs_count) { 936 cs_count = 0; 938 cs_count++; 1023 cs_count [all...] |
H A D | ddr3_dqs.c | 311 u32 uj, cs_count, cs_tmp, ii; local 333 cs_count = 0; 336 cs_count++; 338 sdram_offset = cs_count * (SDRAM_CS_SIZE + 1); 1330 u32 cs, cs_count, cs_tmp, victim_dq; local 1337 cs_count = 0; 1340 cs_count++; 1344 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + 1359 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) +
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H A D | ddr3_pbs.c | 1533 u32 cs, cs_count, cs_tmp; local 1562 cs_count = 0; 1565 cs_count++; 1569 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + 1579 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) +
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H A D | ddr3_init.c | 1053 u32 cs_count = 0; local 1058 cs_count++; 1061 return cs_count;
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/u-boot/drivers/spi/ |
H A D | mpc8xxx_spi.c | 47 int cs_count; member in struct:mpc8xxx_priv 66 priv->cs_count = ret; 142 if (plat->cs >= priv->cs_count) { 143 dev_err(dev, "chip select index %d too large (cs_count=%d)\n", 144 plat->cs, priv->cs_count);
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