Searched refs:cpll_init_cfg (Results 1 - 6 of 6) sorted by relevance

/u-boot/drivers/clk/rockchip/
H A Dclk_rk3066.c82 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); variable in typeref:struct:pll_div
424 rk3066_clk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
H A Dclk_rk3188.c86 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); variable in typeref:struct:pll_div
390 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
H A Dclk_rk3368.c59 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); variable in typeref:struct:pll_div
147 rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
H A Dclk_rk3288.c148 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); variable in typeref:struct:pll_div
441 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
H A Dclk_rk3328.c42 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1); variable in typeref:struct:pll_div
297 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
H A Dclk_rk3399.c58 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); variable in typeref:struct:pll_div
1397 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);

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