Searched refs:cm_base (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-mtmips/mt7621/spl/
H A Dcps.c49 static void cm_init(void __iomem *cm_base) argument
53 gcrcfg = readl(cm_base + GCR_CONFIG);
56 writel((1 << num_cores) - 1, cm_base + GCR_ACCESS);
58 writel(GCR_REG0_BASE_VALUE, cm_base + GCR_REG0_BASE);
59 writel(GCR_REG1_BASE_VALUE, cm_base + GCR_REG1_BASE);
60 writel(GCR_REG2_BASE_VALUE, cm_base + GCR_REG2_BASE);
61 writel(GCR_REG3_BASE_VALUE, cm_base + GCR_REG3_BASE);
63 clrsetbits_32(cm_base + GCR_REG0_MASK,
68 clrsetbits_32(cm_base + GCR_REG1_MASK,
73 clrsetbits_32(cm_base
143 void __iomem *cm_base = (void *)KSEG1ADDR(CONFIG_MIPS_CM_BASE); local
[all...]
/u-boot/arch/mips/mach-mtmips/mt7621/tpl/
H A Dtpl.c58 void __iomem *cm_base = (void *)KSEG1ADDR(CONFIG_MIPS_CM_BASE); local
64 val = readl(cm_base + GCR_BASE);
67 writel(val, cm_base + GCR_BASE);
91 val = readl(cm_base + GCR_BASE);
93 writel(val, cm_base + GCR_BASE);

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