Searched refs:cfg (Results 1 - 25 of 382) sorted by relevance

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/u-boot/drivers/phy/
H A Dphy-core-mipi-dphy.c21 struct phy_configure_opts_mipi_dphy *cfg)
26 if (!cfg)
35 cfg->clk_miss = 0;
36 cfg->clk_post = 60000 + 52 * ui;
37 cfg->clk_pre = 8000;
38 cfg->clk_prepare = 38000;
39 cfg->clk_settle = 95000;
40 cfg->clk_term_en = 0;
41 cfg->clk_trail = 60000;
42 cfg
18 phy_mipi_dphy_get_default_config(unsigned long pixel_clock, unsigned int bpp, unsigned int lanes, struct phy_configure_opts_mipi_dphy *cfg) argument
81 phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg) argument
[all...]
/u-boot/drivers/video/
H A Dssd2828.c154 static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum) argument
156 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
157 return soft_spi_xfer_24bit_3wire(cfg, 0x730000);
163 static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum, argument
166 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
167 soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val);
173 static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum) argument
176 write_hw_register(cfg, SSD2828_PSCR1, 1);
178 write_hw_register(cfg, SSD2828_PDR, cmdnum);
184 static void ssd2828_reset(const struct ssd2828_config *cfg) argument
193 ssd2828_enable_gpio(const struct ssd2828_config *cfg) argument
235 ssd2828_free_gpio(const struct ssd2828_config *cfg) argument
289 ssd2828_configure_video_interface(const struct ssd2828_config *cfg, const struct ctfb_res_modes *mode) argument
340 ssd2828_init(const struct ssd2828_config *cfg, const struct ctfb_res_modes *mode) argument
[all...]
/u-boot/arch/arm/mach-exynos/
H A Dsystem.c36 unsigned int cfg = 0; local
43 cfg = readl(&sysreg->display_ctrl);
44 cfg |= (1 << 1);
45 writel(cfg, &sysreg->display_ctrl);
52 unsigned int cfg = 0; local
59 cfg = readl(&sysreg->disp1blk_cfg);
60 cfg |= (1 << 15);
61 writel(cfg, &sysreg->disp1blk_cfg);
/u-boot/board/Marvell/db-xc3-24g4xg/
H A DMakefile6 extra-y := kwbimage.cfg
11 SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
12 $(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
/u-boot/board/mikrotik/crs3xx-98dx3236/
H A DMakefile6 extra-y := kwbimage.cfg
11 SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
12 $(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
/u-boot/drivers/power/
H A Daxp209.c36 u8 cfg, current; local
46 cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
50 current != cfg) {
51 if (current < cfg)
66 u8 cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); local
73 rc = pmic_bus_write(AXP209_DCDC3_VOLTAGE, cfg);
83 u8 cfg, reg; local
89 cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100);
95 reg |= AXP209_LDO24_LDO2_SET(reg, cfg);
105 u8 cfg; local
170 u8 cfg, reg; local
[all...]
H A Daxp818.c32 u8 cfg = axp818_mvolt_to_cfg(mvolt, 1600, 3400, 100); local
38 ret = pmic_bus_write(AXP818_DCDC1_CTRL, cfg);
49 u8 cfg; local
52 cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20);
54 cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10);
60 ret = pmic_bus_write(AXP818_DCDC2_CTRL, cfg);
71 u8 cfg; local
74 cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20);
76 cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10);
82 ret = pmic_bus_write(AXP818_DCDC3_CTRL, cfg);
93 u8 cfg; local
115 u8 cfg; local
152 u8 cfg; local
175 u8 cfg; local
196 u8 cfg; local
[all...]
H A Daxp809.c32 u8 cfg = axp809_mvolt_to_cfg(mvolt, 1600, 3400, 100); local
38 ret = pmic_bus_write(AXP809_DCDC1_CTRL, cfg);
54 u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20); local
60 ret = pmic_bus_write(AXP809_DCDC2_CTRL, cfg);
71 u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1860, 20); local
77 ret = pmic_bus_write(AXP809_DCDC3_CTRL, cfg);
88 u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20); local
91 cfg = 0x30 + axp809_mvolt_to_cfg(mvolt, 1800, 2600, 100);
97 ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg);
108 u8 cfg local
125 u8 cfg; local
167 u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100); local
190 u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100); local
[all...]
/u-boot/drivers/adc/
H A Dexynos-adc.c41 unsigned int cfg; local
44 cfg = readl(&regs->con2);
45 cfg &= ~ADC_V2_CON2_CHAN_SEL_MASK;
46 cfg |= ADC_V2_CON2_CHAN_SEL(channel);
47 writel(cfg, &regs->con2);
50 cfg = readl(&regs->con1);
51 writel(cfg | ADC_V2_CON1_STC_EN, &regs->con1);
62 unsigned int cfg; local
65 cfg = readl(&regs->con1);
66 cfg
79 unsigned int cfg; local
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/u-boot/include/dt-bindings/dma/
H A Dat91.h35 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
42 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
49 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
/u-boot/arch/microblaze/dts/include/dt-bindings/dma/
H A Dat91.h35 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
42 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
49 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
/u-boot/arch/mips/dts/include/dt-bindings/dma/
H A Dat91.h35 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
42 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
49 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
/u-boot/arch/xtensa/dts/include/dt-bindings/dma/
H A Dat91.h35 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
42 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
49 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
/u-boot/arch/arm/dts/include/dt-bindings/dma/
H A Dat91.h35 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
42 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
49 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
/u-boot/arch/nios2/dts/include/dt-bindings/dma/
H A Dat91.h35 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
42 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
49 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
/u-boot/arch/sandbox/dts/include/dt-bindings/dma/
H A Dat91.h35 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
42 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
49 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
/u-boot/arch/x86/dts/include/dt-bindings/dma/
H A Dat91.h35 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
42 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
49 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
/u-boot/dts/upstream/include/dt-bindings/dma/
H A Dat91.h34 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
41 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
48 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
/u-boot/drivers/soc/ti/
H A Dk3-navss-ringacc-u-boot.c30 writel(0, &ring->cfg->size);
37 val = readl(&ring->cfg->size);
40 writel(val, &ring->cfg->size);
45 writel(0, &ring->cfg->ba_hi);
46 writel(0, &ring->cfg->ba_lo);
47 writel(0, &ring->cfg->size);
54 writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo);
55 writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi);
60 writel(val, &ring->cfg->size);
/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dfsl_ls1_serdes.c43 u32 cfg = in_be32(&gur->rcwsr[4]); local
49 cfg &= RCWSR4_SRDS1_PRTCL_MASK;
50 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
55 cfg &= RCWSR4_SRDS2_PRTCL_MASK;
56 cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT;
64 if (unlikely(cfg == 0))
68 if (serdes_get_prtcl(sd, cfg, i) == device)
79 u32 cfg; local
82 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
83 cfg >>
[all...]
/u-boot/drivers/video/exynos/
H A Dexynos_fb.c107 unsigned int cfg = 0; local
110 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
114 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) |
118 writel(cfg, &reg->dualrgb);
125 unsigned int cfg = 0; local
128 cfg = EXYNOS_DP_CLK_ENABLE;
130 writel(cfg, &reg->dp_mie_clkcon);
137 unsigned int cfg = 0; local
140 cfg = readl((unsigned int)&reg->wincon0 +
143 cfg
207 unsigned int cfg = 0, div = 0, remainder, remainder_div; local
261 unsigned int cfg = 0; local
273 unsigned int cfg = 0; local
288 unsigned int cfg = 0; local
300 unsigned int cfg = 0; local
317 unsigned int cfg = 0; local
327 unsigned int cfg = 0; local
383 unsigned int cfg = 0, rgb_mode; local
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/u-boot/drivers/clk/microchip/
H A Dmpfs_clk_cfg.c54 * @cfg: configuration clock instance
60 struct mpfs_cfg_clock cfg; member in struct:mpfs_cfg_hw_clock
71 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; local
76 val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift;
77 val &= clk_div_mask(cfg->width);
87 struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; local
92 divider_setting = divider_get_val(rate, cfg_hw->prate, cfg->table, cfg
[all...]
/u-boot/drivers/mmc/
H A Dpiton_mmc.c33 struct mmc_config cfg; member in struct:piton_mmc_plat
73 struct mmc_config *cfg; local
78 cfg = &plat->cfg;
79 cfg->name = "PITON MMC";
80 cfg->host_caps = MMC_MODE_8BIT;
81 cfg->f_max = PITON_MMC_DUMMY_F_MAX;
82 cfg->f_min = PITON_MMC_DUMMY_F_MIN;
83 cfg->voltages = MMC_VDD_21_22;
121 struct mmc_config *cfg local
134 struct mmc_config *cfg = &plat->cfg; local
[all...]
/u-boot/drivers/memory/
H A Dti-aemif.c37 static void aemif_configure(int cs, struct aemif_config *cfg) argument
41 if (cfg->mode == AEMIF_MODE_NAND) {
46 } else if (cfg->mode == AEMIF_MODE_ONENAND) {
54 set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
55 set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
56 set_config_field(tmp, WR_SETUP, cfg->wr_setup);
57 set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
58 set_config_field(tmp, WR_HOLD, cfg->wr_hold);
59 set_config_field(tmp, RD_SETUP, cfg->rd_setup);
60 set_config_field(tmp, RD_STROBE, cfg
[all...]
/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c67 int cm_basic_init(const struct cm_config * const cfg) argument
134 writel(cfg->main_vco_base,
136 writel(cfg->peri_vco_base,
138 writel(cfg->sdram_vco_base,
148 writel(cfg->mpuclk,
152 writel(cfg->altera_grp_mpuclk,
156 writel(cfg->mainclk,
160 writel(cfg->dbgatclk,
164 writel(cfg->cfg2fuser0clk,
168 writel(cfg
[all...]

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