Searched refs:adll_tap (Results 1 - 6 of 6) sorted by relevance
| /u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_hw_algo.h | 11 int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
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| H A D | ddr3_training_bist.c | 494 u32 adll_tap; local
520 for (adll_tap = 0; adll_tap < ADLL_TAPS_PER_PERIOD; adll_tap++) {
522 odpg_addr = adll_tap * burst_len;
556 for (adll_tap = 0; adll_tap < ADLL_TAPS_PER_PERIOD; adll_tap++) {
558 DDR_PHY_DATA, CTX_PHY_REG(cs), adll_tap);
560 odpg_addr = adll_tap * burst_le
[all...] |
| H A D | ddr3_training_hw_algo.c | 629 int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap) argument
655 ck_num_adll_tap = ck_delay / adll_tap;
656 ca_num_adll_tap = ca_delay / adll_tap;
667 ("ck_num_adll_tap %d ca_num_adll_tap %d adll_tap %d\n",
668 ck_num_adll_tap, ca_num_adll_tap, adll_tap));
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| H A D | mv_ddr4_training_calibration.c | 1109 int adll_tap = (ONE_MHZ / freq) / ADLL_TAPS_PER_PERIOD; local
1115 int dq_to_dqs_min_delta_threshold = MIN_WL_TO_CTX_ADLL_DIFF + MAX_SKEW_DLY / adll_tap;
1118 u32 pbs_tap_factor0 = PBS_VAL_FACTOR * NOMINAL_PBS_DLY / adll_tap; /* init lambda */
2044 u32 adll_tap; local
2080 for (adll_tap = 0; adll_tap < ADLL_TAPS_PER_PERIOD; adll_tap++) {
2081 idx = subphy * ADLL_TAPS_PER_PERIOD + adll_tap;
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| H A D | ddr3_training.c | 372 u32 bus_cnt = 0, adll_tap = 0; local
698 adll_tap = MEGA / (mv_ddr_freq_get(freq) * 64);
699 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
1240 u32 adll_tap = 0; local
1540 adll_tap = (is_dll_off == 1) ? 1000 : (MEGA / (freq * 64));
1541 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
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| H A D | ddr3_training_pbs.c | 39 int adll_tap = MEGA / mv_ddr_freq_get(medium_freq) / 64; local
790 adll_tap /
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Completed in 71 milliseconds