Searched refs:TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT (Results 1 - 1 of 1) sorted by relevance

/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h1883 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12 macro
1884 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK)

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