Searched refs:REG_DDR_TIMING_CFG_4 (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/arm/include/asm/arch-imx9/
H A Dddr.h22 #define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160) macro
/u-boot/drivers/ddr/imx/imx9/
H A Dddr_init.c201 REG_DDR_TIMING_CFG_4);
205 REG_DDR_TIMING_CFG_4);
254 REG_DDR_TIMING_CFG_4, tmp_t);
261 REG_DDR_TIMING_CFG_4, tmp_t);

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