Searched refs:PHY_CON0_CTRL_DDR_MODE_MASK (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddmc.h466 #define PHY_CON0_CTRL_DDR_MODE_MASK 0x3 macro
/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c492 val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
497 val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);

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