Searched refs:MVPP2_CPU_D_CACHE_LINE_SIZE (Results 1 - 1 of 1) sorted by relevance

/u-boot/drivers/net/
H A Dmvpp2.c67 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
567 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32 macro
635 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
4071 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4110 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4195 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));

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