Searched refs:MSR_PMG_CST_CONFIG_CONTROL (Results 1 - 4 of 4) sorted by relevance

/u-boot/arch/x86/cpu/baytrail/
H A Dcpu.c113 msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f000f, 0xe0008),
/u-boot/arch/x86/cpu/apollolake/
H A Dcpu.c119 wrmsrl(MSR_PMG_CST_CONFIG_CONTROL,
/u-boot/arch/x86/cpu/broadwell/
H A Dcpu_full.c419 msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
429 msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
/u-boot/arch/x86/include/asm/
H A Dmsr-index.h70 #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 macro
71 /* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
73 /* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
75 /* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
77 /* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */

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