Searched refs:LOCK (Results 1 - 8 of 8) sorted by relevance

/u-boot/arch/arm/mach-zynqmp/
H A Dmp.c16 #define LOCK 0 macro
68 if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
77 if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
92 if (mode == LOCK) {
110 if (mode == LOCK) {
134 if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
138 if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
166 return LOCK;
251 set_r5_tcm_mode(LOCK);
252 set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK);
[all...]
/u-boot/drivers/watchdog/
H A Dsp805_wdt.c33 #define LOCK 0x00000001 macro
49 writel(LOCK, priv->reg + WDTLOCK);
82 writel(LOCK, priv->reg + WDTLOCK);
94 writel(LOCK, priv->reg + WDTLOCK);
/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_px30.h51 #define LOCK(n) (((n) >> 10) & 0x1) macro
H A Dsdram_rk3328.h71 #define LOCK(n) (((n) >> 10) & 0x1) macro
H A Dsdram_rv1126.h221 #define LOCK(n) (((n) >> 10) & 0x1) macro
/u-boot/drivers/ram/rockchip/
H A Dsdram_px30.c189 if (LOCK(readl(&dram->cru->pll[1].con1)))
H A Dsdram_rk3328.c111 if (LOCK(readl(&dram->cru->dpll_con[1])))
H A Dsdram_rv1126.c357 if (LOCK(readl(&dram->cru->pll[1].con1)))

Completed in 174 milliseconds