Searched refs:IRTL_1024_NS (Results 1 - 4 of 4) sorted by relevance

/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dmodel_206ax.h35 #define IRTL_1024_NS (2 << 10) macro
/u-boot/arch/x86/cpu/broadwell/
H A Dcpu_full.c443 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
448 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
453 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
458 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
463 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
468 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
/u-boot/arch/x86/cpu/ivybridge/
H A Dmodel_206ax.c255 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
260 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
265 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
/u-boot/arch/x86/include/asm/
H A Dmsr-index.h251 #define IRTL_1024_NS (2 << 10) macro

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