Searched refs:DDR_CTRL_UPD_MRS (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-ath79/ar933x/
H A Dddr.c19 #define DDR_CTRL_UPD_MRS BIT(0) macro
146 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
158 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
198 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
213 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c20 #define DDR_CTRL_UPD_MRS BIT(0) macro
271 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
289 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
361 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
379 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);

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