Searched refs:DDR_CTRL_UPD_EMRS (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-ath79/ar933x/
H A Dddr.c18 #define DDR_CTRL_UPD_EMRS BIT(1) macro
140 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
164 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
169 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
204 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c19 #define DDR_CTRL_UPD_EMRS BIT(1) macro
263 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
353 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
387 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
395 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);

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