Searched refs:DDR_CTL_BASE (Results 1 - 1 of 1) sorted by relevance

/u-boot/arch/arm/include/asm/arch-imx9/
H A Dddr.h12 #define DDR_CTL_BASE 0x4E300000 macro
16 #define REG_DDR_SDRAM_MD_CNTL (DDR_CTL_BASE + 0x120)
17 #define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0)
18 #define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8)
19 #define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
20 #define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
21 #define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
22 #define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
23 #define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
24 #define REG_DDR_SDRAM_CFG_3 (DDR_CTL_BASE
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