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/u-boot/board/highbank/
H A D	ahci.c	`20 #define CR_BUSY 0x0001 macro 61 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) 65 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) 75 while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)`

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