| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 53 #define CLK_TOP_UART_SEL 30 macro
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| H A D | mt8135-clk.h | 88 #define CLK_TOP_UART_SEL 77 macro
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| H A D | mediatek,mt7981-clk.h | 93 #define CLK_TOP_UART_SEL 80 macro
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| H A D | mt7629-clk.h | 91 #define CLK_TOP_UART_SEL 81 macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 95 #define CLK_TOP_UART_SEL 81 macro
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| H A D | mt8512-clk.h | 71 #define CLK_TOP_UART_SEL 60 macro
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| H A D | mt7622-clk.h | 77 #define CLK_TOP_UART_SEL 64 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 95 #define CLK_TOP_UART_SEL 81 macro
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| H A D | mt8512-clk.h | 71 #define CLK_TOP_UART_SEL 60 macro
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| H A D | mt7622-clk.h | 77 #define CLK_TOP_UART_SEL 64 macro
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| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 95 #define CLK_TOP_UART_SEL 81 macro
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| H A D | mt8512-clk.h | 71 #define CLK_TOP_UART_SEL 60 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 95 #define CLK_TOP_UART_SEL 81 macro
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| H A D | mt8512-clk.h | 71 #define CLK_TOP_UART_SEL 60 macro
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| H A D | mt7622-clk.h | 77 #define CLK_TOP_UART_SEL 64 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 95 #define CLK_TOP_UART_SEL 81 macro
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| H A D | mt8512-clk.h | 71 #define CLK_TOP_UART_SEL 60 macro
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| H A D | mt7622-clk.h | 77 #define CLK_TOP_UART_SEL 64 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 95 #define CLK_TOP_UART_SEL 81 macro
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| H A D | mt8512-clk.h | 71 #define CLK_TOP_UART_SEL 60 macro
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| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 95 #define CLK_TOP_UART_SEL 81 macro
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| H A D | mt8512-clk.h | 71 #define CLK_TOP_UART_SEL 60 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 95 #define CLK_TOP_UART_SEL 81 macro
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| H A D | mt8512-clk.h | 71 #define CLK_TOP_UART_SEL 60 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 435 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7),
627 GATE_IFR2(CLK_IFR_UART0, CLK_TOP_UART_SEL, 22),
628 GATE_IFR2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23),
629 GATE_IFR2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24),
630 GATE_IFR2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26),
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