Searched refs:CLK_TOP_SYSPLL4_D4 (Results 1 - 25 of 45) sorted by relevance

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/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7629-clk.h50 #define CLK_TOP_SYSPLL4_D4 37 macro
H A Dmt7622-clk.h40 #define CLK_TOP_SYSPLL4_D4 28 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7629-clk.h50 #define CLK_TOP_SYSPLL4_D4 37 macro
H A Dmt7622-clk.h40 #define CLK_TOP_SYSPLL4_D4 28 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7629-clk.h50 #define CLK_TOP_SYSPLL4_D4 37 macro
H A Dmt7622-clk.h40 #define CLK_TOP_SYSPLL4_D4 28 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7629-clk.h50 #define CLK_TOP_SYSPLL4_D4 37 macro
H A Dmt7622-clk.h40 #define CLK_TOP_SYSPLL4_D4 28 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7629-clk.h50 #define CLK_TOP_SYSPLL4_D4 37 macro
H A Dmt7622-clk.h40 #define CLK_TOP_SYSPLL4_D4 28 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7629-clk.h50 #define CLK_TOP_SYSPLL4_D4 37 macro
H A Dmt7622-clk.h40 #define CLK_TOP_SYSPLL4_D4 28 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7629-clk.h50 #define CLK_TOP_SYSPLL4_D4 37 macro
H A Dmt7622-clk.h40 #define CLK_TOP_SYSPLL4_D4 28 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7629-clk.h50 #define CLK_TOP_SYSPLL4_D4 37 macro
H A Dmt7622-clk.h40 #define CLK_TOP_SYSPLL4_D4 28 macro
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt7629-clk.h47 #define CLK_TOP_SYSPLL4_D4 37 macro
H A Dmediatek,mt6795-clk.h64 #define CLK_TOP_SYSPLL4_D4 53 macro
H A Dmt6765-clk.h50 #define CLK_TOP_SYSPLL4_D4 15 macro
H A Dmt6797-clk.h61 #define CLK_TOP_SYSPLL4_D4 51 macro
H A Dmt7622-clk.h40 #define CLK_TOP_SYSPLL4_D4 28 macro
H A Dmt8173-clk.h66 #define CLK_TOP_SYSPLL4_D4 56 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt8365.c94 PLL_FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", CLK_APMIXED_MAINPLL, 1, 28),
250 CLK_TOP_SYSPLL4_D4,
393 CLK_TOP_SYSPLL4_D4,
H A Dclk-mt7622.c111 FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
230 CLK_TOP_SYSPLL4_D4,
282 CLK_TOP_SYSPLL4_D4,
H A Dclk-mt7629.c114 FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
244 CLK_TOP_SYSPLL4_D4,
282 CLK_TOP_SYSPLL4_D4,

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