| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 104 FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
137 FACTOR1(CLK_TOP_AP2WBHIF_HCLK, CLK_TOP_SYSPLL1_D8, 1, 1),
170 CLK_TOP_SYSPLL1_D8
203 CLK_TOP_SYSPLL1_D8,
272 CLK_TOP_SYSPLL1_D8,
295 CLK_TOP_SYSPLL1_D8,
306 CLK_TOP_SYSPLL1_D8,
335 CLK_TOP_SYSPLL1_D8
|
| H A D | clk-mt8365.c | 83 PLL_FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", CLK_APMIXED_MAINPLL, 1, 16),
298 CLK_TOP_SYSPLL1_D8
310 CLK_TOP_SYSPLL1_D8
317 CLK_TOP_SYSPLL1_D8,
324 CLK_TOP_SYSPLL1_D8
394 CLK_TOP_SYSPLL1_D8,
|
| H A D | clk-mt8512.c | 79 FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
139 CLK_TOP_SYSPLL1_D8,
278 CLK_TOP_SYSPLL1_D8
286 CLK_TOP_SYSPLL1_D8,
294 CLK_TOP_SYSPLL1_D8,
326 CLK_TOP_SYSPLL1_D8,
438 CLK_TOP_SYSPLL1_D8,
|
| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 40 #define CLK_TOP_SYSPLL1_D8 27 macro
|
| H A D | mt8512-clk.h | 15 #define CLK_TOP_SYSPLL1_D8 4 macro
|
| H A D | mt7622-clk.h | 33 #define CLK_TOP_SYSPLL1_D8 21 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 40 #define CLK_TOP_SYSPLL1_D8 27 macro
|
| H A D | mt8512-clk.h | 15 #define CLK_TOP_SYSPLL1_D8 4 macro
|
| H A D | mt7622-clk.h | 33 #define CLK_TOP_SYSPLL1_D8 21 macro
|
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 40 #define CLK_TOP_SYSPLL1_D8 27 macro
|
| H A D | mt8512-clk.h | 15 #define CLK_TOP_SYSPLL1_D8 4 macro
|
| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 40 #define CLK_TOP_SYSPLL1_D8 27 macro
|
| H A D | mt8512-clk.h | 15 #define CLK_TOP_SYSPLL1_D8 4 macro
|
| H A D | mt7622-clk.h | 33 #define CLK_TOP_SYSPLL1_D8 21 macro
|
| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 40 #define CLK_TOP_SYSPLL1_D8 27 macro
|
| H A D | mt8512-clk.h | 15 #define CLK_TOP_SYSPLL1_D8 4 macro
|
| H A D | mt7622-clk.h | 33 #define CLK_TOP_SYSPLL1_D8 21 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 40 #define CLK_TOP_SYSPLL1_D8 27 macro
|
| H A D | mt8512-clk.h | 15 #define CLK_TOP_SYSPLL1_D8 4 macro
|
| H A D | mt7622-clk.h | 33 #define CLK_TOP_SYSPLL1_D8 21 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 40 #define CLK_TOP_SYSPLL1_D8 27 macro
|
| H A D | mt8512-clk.h | 15 #define CLK_TOP_SYSPLL1_D8 4 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 40 #define CLK_TOP_SYSPLL1_D8 27 macro
|
| H A D | mt8512-clk.h | 15 #define CLK_TOP_SYSPLL1_D8 4 macro
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 37 #define CLK_TOP_SYSPLL1_D8 27 macro
|