| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 81 PLL_FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", CLK_APMIXED_MAINPLL, 1, 4),
148 CLK_TOP_SYSPLL1_D2
154 CLK_TOP_SYSPLL1_D2,
166 CLK_TOP_SYSPLL1_D2,
182 CLK_TOP_SYSPLL1_D2
209 CLK_TOP_SYSPLL1_D2,
218 CLK_TOP_SYSPLL1_D2,
230 CLK_TOP_SYSPLL1_D2,
296 CLK_TOP_SYSPLL1_D2,
340 CLK_TOP_SYSPLL1_D2
[all...] |
| H A D | clk-mt7629.c | 102 FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
154 CLK_TOP_SYSPLL1_D2,
175 CLK_TOP_SYSPLL1_D2,
270 CLK_TOP_SYSPLL1_D2,
313 CLK_TOP_SYSPLL1_D2,
319 CLK_TOP_SYSPLL1_D2,
351 CLK_TOP_SYSPLL1_D2,
|
| H A D | clk-mt7622.c | 102 FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
143 CLK_TOP_SYSPLL1_D2,
163 CLK_TOP_SYSPLL1_D2,
252 CLK_TOP_SYSPLL1_D2,
275 CLK_TOP_SYSPLL1_D2,
|
| H A D | clk-mt7623.c | 107 FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
189 CLK_TOP_SYSPLL1_D2,
211 CLK_TOP_SYSPLL1_D2,
373 CLK_TOP_SYSPLL1_D2,
399 CLK_TOP_SYSPLL1_D2,
440 CLK_TOP_SYSPLL1_D2,
456 CLK_TOP_SYSPLL1_D2,
|
| H A D | clk-mt8512.c | 77 FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
180 CLK_TOP_SYSPLL1_D2,
201 CLK_TOP_SYSPLL1_D2,
345 CLK_TOP_SYSPLL1_D2,
398 CLK_TOP_SYSPLL1_D2,
408 CLK_TOP_SYSPLL1_D2,
787 .fdivs_offs = CLK_TOP_SYSPLL1_D2,
|
| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 38 #define CLK_TOP_SYSPLL1_D2 25 macro
|
| H A D | mt8512-clk.h | 13 #define CLK_TOP_SYSPLL1_D2 2 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 38 #define CLK_TOP_SYSPLL1_D2 25 macro
|
| H A D | mt8512-clk.h | 13 #define CLK_TOP_SYSPLL1_D2 2 macro
|
| H A D | mt7622-clk.h | 31 #define CLK_TOP_SYSPLL1_D2 19 macro
|
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 38 #define CLK_TOP_SYSPLL1_D2 25 macro
|
| H A D | mt8512-clk.h | 13 #define CLK_TOP_SYSPLL1_D2 2 macro
|
| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 38 #define CLK_TOP_SYSPLL1_D2 25 macro
|
| H A D | mt8512-clk.h | 13 #define CLK_TOP_SYSPLL1_D2 2 macro
|
| H A D | mt7622-clk.h | 31 #define CLK_TOP_SYSPLL1_D2 19 macro
|
| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 38 #define CLK_TOP_SYSPLL1_D2 25 macro
|
| H A D | mt8512-clk.h | 13 #define CLK_TOP_SYSPLL1_D2 2 macro
|
| H A D | mt7622-clk.h | 31 #define CLK_TOP_SYSPLL1_D2 19 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 38 #define CLK_TOP_SYSPLL1_D2 25 macro
|
| H A D | mt8512-clk.h | 13 #define CLK_TOP_SYSPLL1_D2 2 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 38 #define CLK_TOP_SYSPLL1_D2 25 macro
|
| H A D | mt8512-clk.h | 13 #define CLK_TOP_SYSPLL1_D2 2 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 38 #define CLK_TOP_SYSPLL1_D2 25 macro
|
| H A D | mt8512-clk.h | 13 #define CLK_TOP_SYSPLL1_D2 2 macro
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 35 #define CLK_TOP_SYSPLL1_D2 25 macro
|