Searched refs:CLK_TOP_SSUSB_XHCI_SEL (Results 1 - 20 of 20) sorted by relevance
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 92 #define CLK_TOP_SSUSB_XHCI_SEL 81 macro
|
| H A D | mediatek,mt8365-clk.h | 96 #define CLK_TOP_SSUSB_XHCI_SEL 86 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 92 #define CLK_TOP_SSUSB_XHCI_SEL 81 macro
|
| H A D | mediatek,mt8365-clk.h | 96 #define CLK_TOP_SSUSB_XHCI_SEL 86 macro
|
| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 92 #define CLK_TOP_SSUSB_XHCI_SEL 81 macro
|
| H A D | mediatek,mt8365-clk.h | 96 #define CLK_TOP_SSUSB_XHCI_SEL 86 macro
|
| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 92 #define CLK_TOP_SSUSB_XHCI_SEL 81 macro
|
| H A D | mediatek,mt8365-clk.h | 96 #define CLK_TOP_SSUSB_XHCI_SEL 86 macro
|
| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 92 #define CLK_TOP_SSUSB_XHCI_SEL 81 macro
|
| H A D | mediatek,mt8365-clk.h | 96 #define CLK_TOP_SSUSB_XHCI_SEL 86 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 92 #define CLK_TOP_SSUSB_XHCI_SEL 81 macro
|
| H A D | mediatek,mt8365-clk.h | 96 #define CLK_TOP_SSUSB_XHCI_SEL 86 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 92 #define CLK_TOP_SSUSB_XHCI_SEL 81 macro
|
| H A D | mediatek,mt8365-clk.h | 96 #define CLK_TOP_SSUSB_XHCI_SEL 86 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 92 #define CLK_TOP_SSUSB_XHCI_SEL 81 macro
|
| H A D | mediatek,mt8365-clk.h | 96 #define CLK_TOP_SSUSB_XHCI_SEL 86 macro
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 96 #define CLK_TOP_SSUSB_XHCI_SEL 86 macro
|
| H A D | mt8192-clk.h | 47 #define CLK_TOP_SSUSB_XHCI_SEL 35 macro
|
| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 456 MUX_GATE(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23),
685 GATE_IFR6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
|
| H A D | clk-mt8512.c | 524 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents,
781 GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
|
Completed in 445 milliseconds