Searched refs:CLK_TOP_SLOW_MFG_SEL (Results 1 - 10 of 10) sorted by relevance

/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt8167-clk.h66 #define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42) macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h92 #define CLK_TOP_SLOW_MFG_SEL 68 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h92 #define CLK_TOP_SLOW_MFG_SEL 68 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h92 #define CLK_TOP_SLOW_MFG_SEL 68 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h92 #define CLK_TOP_SLOW_MFG_SEL 68 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h92 #define CLK_TOP_SLOW_MFG_SEL 68 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h92 #define CLK_TOP_SLOW_MFG_SEL 68 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h92 #define CLK_TOP_SLOW_MFG_SEL 68 macro
/u-boot/include/dt-bindings/clock/
H A Dmt8516-clk.h92 #define CLK_TOP_SLOW_MFG_SEL 68 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt8516.c516 MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
702 GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),

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