Searched refs:CLK_TOP_SENIF_SEL (Results 1 - 10 of 10) sorted by relevance
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 100 #define CLK_TOP_SENIF_SEL 90 macro
|
| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 100 #define CLK_TOP_SENIF_SEL 90 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 100 #define CLK_TOP_SENIF_SEL 90 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 100 #define CLK_TOP_SENIF_SEL 90 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 100 #define CLK_TOP_SENIF_SEL 90 macro
|
| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 100 #define CLK_TOP_SENIF_SEL 90 macro
|
| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 100 #define CLK_TOP_SENIF_SEL 90 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 100 #define CLK_TOP_SENIF_SEL 90 macro
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 100 #define CLK_TOP_SENIF_SEL 90 macro
|
| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 461 MUX_GATE(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23),
|
Completed in 365 milliseconds