null

Sort by

In Project(s)

Searched refs:CLK_TOP_PCIE0_MCU_SEL (Results 1 - 10 of 10) sorted by relevance

/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A D	mt7629-clk.h	`116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro`
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A D	mt7629-clk.h	`116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro`
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A D	mt7629-clk.h	`116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro`
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A D	mt7629-clk.h	`116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro`
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A D	mt7629-clk.h	`116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro`
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A D	mt7629-clk.h	`116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro`
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A D	mt7629-clk.h	`116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro`
/u-boot/include/dt-bindings/clock/
H A D	mt7629-clk.h	`116 #define CLK_TOP_PCIE0_MCU_SEL 102 macro`
/u-boot/dts/upstream/include/dt-bindings/clock/
H A D	mt7629-clk.h	`112 #define CLK_TOP_PCIE0_MCU_SEL 102 macro`
/u-boot/drivers/clk/mediatek/
H A D	clk-mt7629.c	`409 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15),`

Completed in 246 milliseconds