Searched refs:CLK_TOP_P0_1MHZ (Results 1 - 20 of 20) sorted by relevance
| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 26 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 26 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 26 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 26 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 26 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 26 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 26 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 26 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 23 #define CLK_TOP_P0_1MHZ 13 macro
|
| H A D | mt7622-clk.h | 25 #define CLK_TOP_P0_1MHZ 13 macro
|
| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7622.c | 96 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
477 GATE_PCIE(CLK_PCIE_P0_AUX_EN, CLK_TOP_P0_1MHZ, 18),
|
| H A D | clk-mt7629.c | 90 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
|
Completed in 360 milliseconds