Searched refs:CLK_TOP_NR_SEL (Results 1 - 11 of 11) sorted by relevance

/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h129 #define CLK_TOP_NR_SEL 115 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h129 #define CLK_TOP_NR_SEL 115 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h129 #define CLK_TOP_NR_SEL 115 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h129 #define CLK_TOP_NR_SEL 115 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h129 #define CLK_TOP_NR_SEL 115 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h129 #define CLK_TOP_NR_SEL 115 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h129 #define CLK_TOP_NR_SEL 115 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h129 #define CLK_TOP_NR_SEL 115 macro
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt2701-clk.h114 #define CLK_TOP_NR_SEL 103 macro
H A Dmt2712-clk.h152 #define CLK_TOP_NR_SEL 121 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c546 MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23),

Completed in 157 milliseconds