Searched refs:CLK_TOP_MSDC2_2_HC_SEL (Results 1 - 19 of 19) sorted by relevance
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 75 #define CLK_TOP_MSDC2_2_HC_SEL 64 macro
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| H A D | mediatek,mt8365-clk.h | 82 #define CLK_TOP_MSDC2_2_HC_SEL 72 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 75 #define CLK_TOP_MSDC2_2_HC_SEL 64 macro
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| H A D | mediatek,mt8365-clk.h | 82 #define CLK_TOP_MSDC2_2_HC_SEL 72 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 75 #define CLK_TOP_MSDC2_2_HC_SEL 64 macro
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| H A D | mediatek,mt8365-clk.h | 82 #define CLK_TOP_MSDC2_2_HC_SEL 72 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 75 #define CLK_TOP_MSDC2_2_HC_SEL 64 macro
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| H A D | mediatek,mt8365-clk.h | 82 #define CLK_TOP_MSDC2_2_HC_SEL 72 macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 75 #define CLK_TOP_MSDC2_2_HC_SEL 64 macro
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| H A D | mediatek,mt8365-clk.h | 82 #define CLK_TOP_MSDC2_2_HC_SEL 72 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 75 #define CLK_TOP_MSDC2_2_HC_SEL 64 macro
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| H A D | mediatek,mt8365-clk.h | 82 #define CLK_TOP_MSDC2_2_HC_SEL 72 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 75 #define CLK_TOP_MSDC2_2_HC_SEL 64 macro
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| H A D | mediatek,mt8365-clk.h | 82 #define CLK_TOP_MSDC2_2_HC_SEL 72 macro
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| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 75 #define CLK_TOP_MSDC2_2_HC_SEL 64 macro
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| H A D | mediatek,mt8365-clk.h | 82 #define CLK_TOP_MSDC2_2_HC_SEL 72 macro
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 82 #define CLK_TOP_MSDC2_2_HC_SEL 72 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 438 MUX_GATE(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31),
637 GATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_MSDC2_2_HC_SEL, 3),
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| H A D | clk-mt8512.c | 469 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents,
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