Searched refs:CLK_TOP_MFG_MM_SEL (Results 1 - 10 of 10) sorted by relevance

/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt8167-clk.h59 #define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35) macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h85 #define CLK_TOP_MFG_MM_SEL 61 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h85 #define CLK_TOP_MFG_MM_SEL 61 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h85 #define CLK_TOP_MFG_MM_SEL 61 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h85 #define CLK_TOP_MFG_MM_SEL 61 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h85 #define CLK_TOP_MFG_MM_SEL 61 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h85 #define CLK_TOP_MFG_MM_SEL 61 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt8516-clk.h85 #define CLK_TOP_MFG_MM_SEL 61 macro
/u-boot/include/dt-bindings/clock/
H A Dmt8516-clk.h85 #define CLK_TOP_MFG_MM_SEL 61 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt8516.c508 MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
636 GATE_TOP0(CLK_TOP_MFG_MM, CLK_TOP_MFG_MM_SEL, 2),

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