Searched refs:CLK_TOP_LVDSPLL_D8 (Results 1 - 14 of 14) sorted by relevance

/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt8135-clk.h64 #define CLK_TOP_LVDSPLL_D8 53 macro
H A Dmt8167-clk.h31 #define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7) macro
H A Dmt8173-clk.h44 #define CLK_TOP_LVDSPLL_D8 34 macro
H A Dmediatek,mt8365-clk.h47 #define CLK_TOP_LVDSPLL_D8 37 macro
H A Dmt2712-clk.h87 #define CLK_TOP_LVDSPLL_D8 56 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h47 #define CLK_TOP_LVDSPLL_D8 37 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h47 #define CLK_TOP_LVDSPLL_D8 37 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h47 #define CLK_TOP_LVDSPLL_D8 37 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h47 #define CLK_TOP_LVDSPLL_D8 37 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h47 #define CLK_TOP_LVDSPLL_D8 37 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h47 #define CLK_TOP_LVDSPLL_D8 37 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h47 #define CLK_TOP_LVDSPLL_D8 37 macro
/u-boot/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h47 #define CLK_TOP_LVDSPLL_D8 37 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt8365.c112 PLL_FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", CLK_APMIXED_LVDSPLL, 1, 8),
347 CLK_TOP_LVDSPLL_D8,

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