Searched refs:CLK_TOP_IP0_NNA_SEL (Results 1 - 9 of 9) sorted by relevance

/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt8512-clk.h103 #define CLK_TOP_IP0_NNA_SEL 92 macro
/u-boot/include/dt-bindings/clock/
H A Dmt8512-clk.h103 #define CLK_TOP_IP0_NNA_SEL 92 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt8512-clk.h103 #define CLK_TOP_IP0_NNA_SEL 92 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt8512-clk.h103 #define CLK_TOP_IP0_NNA_SEL 92 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt8512-clk.h103 #define CLK_TOP_IP0_NNA_SEL 92 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt8512-clk.h103 #define CLK_TOP_IP0_NNA_SEL 92 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt8512-clk.h103 #define CLK_TOP_IP0_NNA_SEL 92 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt8512-clk.h103 #define CLK_TOP_IP0_NNA_SEL 92 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt8512.c560 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents,

Completed in 115 milliseconds