Searched refs:CLK_TOP_DSP_SEL (Results 1 - 19 of 19) sorted by relevance
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 96 #define CLK_TOP_DSP_SEL 85 macro
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| H A D | mediatek,mt8365-clk.h | 105 #define CLK_TOP_DSP_SEL 95 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 96 #define CLK_TOP_DSP_SEL 85 macro
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| H A D | mediatek,mt8365-clk.h | 105 #define CLK_TOP_DSP_SEL 95 macro
|
| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 96 #define CLK_TOP_DSP_SEL 85 macro
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| H A D | mediatek,mt8365-clk.h | 105 #define CLK_TOP_DSP_SEL 95 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 96 #define CLK_TOP_DSP_SEL 85 macro
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| H A D | mediatek,mt8365-clk.h | 105 #define CLK_TOP_DSP_SEL 95 macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 96 #define CLK_TOP_DSP_SEL 85 macro
|
| H A D | mediatek,mt8365-clk.h | 105 #define CLK_TOP_DSP_SEL 95 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 96 #define CLK_TOP_DSP_SEL 85 macro
|
| H A D | mediatek,mt8365-clk.h | 105 #define CLK_TOP_DSP_SEL 95 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 96 #define CLK_TOP_DSP_SEL 85 macro
|
| H A D | mediatek,mt8365-clk.h | 105 #define CLK_TOP_DSP_SEL 95 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 96 #define CLK_TOP_DSP_SEL 85 macro
|
| H A D | mediatek,mt8365-clk.h | 105 #define CLK_TOP_DSP_SEL 95 macro
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 105 #define CLK_TOP_DSP_SEL 95 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 467 MUX_GATE(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31),
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| H A D | clk-mt8512.c | 537 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents,
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Completed in 159 milliseconds