Searched refs:CLK_TOP_DSPPLL_D2 (Results 1 - 19 of 19) sorted by relevance
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 63 #define CLK_TOP_DSPPLL_D2 52 macro
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| H A D | mediatek,mt8365-clk.h | 66 #define CLK_TOP_DSPPLL_D2 56 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 63 #define CLK_TOP_DSPPLL_D2 52 macro
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| H A D | mediatek,mt8365-clk.h | 66 #define CLK_TOP_DSPPLL_D2 56 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 63 #define CLK_TOP_DSPPLL_D2 52 macro
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| H A D | mediatek,mt8365-clk.h | 66 #define CLK_TOP_DSPPLL_D2 56 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 63 #define CLK_TOP_DSPPLL_D2 52 macro
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| H A D | mediatek,mt8365-clk.h | 66 #define CLK_TOP_DSPPLL_D2 56 macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 63 #define CLK_TOP_DSPPLL_D2 52 macro
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| H A D | mediatek,mt8365-clk.h | 66 #define CLK_TOP_DSPPLL_D2 56 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 63 #define CLK_TOP_DSPPLL_D2 52 macro
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| H A D | mediatek,mt8365-clk.h | 66 #define CLK_TOP_DSPPLL_D2 56 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 63 #define CLK_TOP_DSPPLL_D2 52 macro
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| H A D | mediatek,mt8365-clk.h | 66 #define CLK_TOP_DSPPLL_D2 56 macro
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| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 63 #define CLK_TOP_DSPPLL_D2 52 macro
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| H A D | mediatek,mt8365-clk.h | 66 #define CLK_TOP_DSPPLL_D2 56 macro
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 66 #define CLK_TOP_DSPPLL_D2 56 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 130 PLL_FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", CLK_APMIXED_DSPPLL, 1, 2),
355 CLK_TOP_DSPPLL_D2,
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| H A D | clk-mt8512.c | 127 FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2),
303 CLK_TOP_DSPPLL_D2,
364 CLK_TOP_DSPPLL_D2,
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