Searched refs:CLK_TOP_CAMTG_SEL (Results 1 - 25 of 26) sorted by relevance
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 90 #define CLK_TOP_CAMTG_SEL 79 macro
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| H A D | mediatek,mt6795-clk.h | 98 #define CLK_TOP_CAMTG_SEL 87 macro
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| H A D | mt6765-clk.h | 137 #define CLK_TOP_CAMTG_SEL 102 macro
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| H A D | mt8173-clk.h | 100 #define CLK_TOP_CAMTG_SEL 90 macro
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| H A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
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| H A D | mt2701-clk.h | 91 #define CLK_TOP_CAMTG_SEL 80 macro
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| H A D | mt2712-clk.h | 137 #define CLK_TOP_CAMTG_SEL 106 macro
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| H A D | mt8192-clk.h | 27 #define CLK_TOP_CAMTG_SEL 15 macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 108 #define CLK_TOP_CAMTG_SEL 94 macro
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| H A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 108 #define CLK_TOP_CAMTG_SEL 94 macro
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| H A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
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| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 108 #define CLK_TOP_CAMTG_SEL 94 macro
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| H A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 108 #define CLK_TOP_CAMTG_SEL 94 macro
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| H A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 108 #define CLK_TOP_CAMTG_SEL 94 macro
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| H A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 108 #define CLK_TOP_CAMTG_SEL 94 macro
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| H A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
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| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 108 #define CLK_TOP_CAMTG_SEL 94 macro
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| H A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 108 #define CLK_TOP_CAMTG_SEL 94 macro
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| H A D | mediatek,mt8365-clk.h | 77 #define CLK_TOP_CAMTG_SEL 67 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 432 MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23),
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