Searched refs:CLK_TOP_AUD_K5_SRC_SEL (Results 1 - 10 of 10) sorted by relevance

/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h153 #define CLK_TOP_AUD_K5_SRC_SEL 139 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h153 #define CLK_TOP_AUD_K5_SRC_SEL 139 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h153 #define CLK_TOP_AUD_K5_SRC_SEL 139 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h153 #define CLK_TOP_AUD_K5_SRC_SEL 139 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h153 #define CLK_TOP_AUD_K5_SRC_SEL 139 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h153 #define CLK_TOP_AUD_K5_SRC_SEL 139 macro
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7623-clk.h153 #define CLK_TOP_AUD_K5_SRC_SEL 139 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h153 #define CLK_TOP_AUD_K5_SRC_SEL 139 macro
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt2701-clk.h138 #define CLK_TOP_AUD_K5_SRC_SEL 127 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c578 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),

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