Searched refs:CLK_TOP_AUD_ENGEN2_SEL (Results 1 - 21 of 21) sorted by relevance
| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 96 #define CLK_TOP_AUD_ENGEN2_SEL 72 macro
|
| H A D | mediatek,mt8365-clk.h | 91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 96 #define CLK_TOP_AUD_ENGEN2_SEL 72 macro
|
| H A D | mediatek,mt8365-clk.h | 91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
|
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 96 #define CLK_TOP_AUD_ENGEN2_SEL 72 macro
|
| H A D | mediatek,mt8365-clk.h | 91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
|
| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 96 #define CLK_TOP_AUD_ENGEN2_SEL 72 macro
|
| H A D | mediatek,mt8365-clk.h | 91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
|
| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 96 #define CLK_TOP_AUD_ENGEN2_SEL 72 macro
|
| H A D | mediatek,mt8365-clk.h | 91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 96 #define CLK_TOP_AUD_ENGEN2_SEL 72 macro
|
| H A D | mediatek,mt8365-clk.h | 91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 96 #define CLK_TOP_AUD_ENGEN2_SEL 72 macro
|
| H A D | mediatek,mt8365-clk.h | 91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 96 #define CLK_TOP_AUD_ENGEN2_SEL 72 macro
|
| H A D | mediatek,mt8365-clk.h | 91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 179 #define CLK_TOP_AUD_ENGEN2_SEL 147 macro
|
| H A D | mediatek,mt8365-clk.h | 91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
|
| H A D | mt8192-clk.h | 56 #define CLK_TOP_AUD_ENGEN2_SEL 44 macro
|
| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8516.c | 520 MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
706 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
|
| H A D | clk-mt8365.c | 450 MUX_GATE(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7),
|
Completed in 198 milliseconds