Searched refs:CLK_TOP_AUD_ENGEN1_SEL (Results 1 - 22 of 22) sorted by relevance
/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt8516-clk.h | 95 #define CLK_TOP_AUD_ENGEN1_SEL 71 macro
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H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt8516-clk.h | 95 #define CLK_TOP_AUD_ENGEN1_SEL 71 macro
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H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt8516-clk.h | 95 #define CLK_TOP_AUD_ENGEN1_SEL 71 macro
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H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt8516-clk.h | 95 #define CLK_TOP_AUD_ENGEN1_SEL 71 macro
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H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt8516-clk.h | 95 #define CLK_TOP_AUD_ENGEN1_SEL 71 macro
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H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt8516-clk.h | 95 #define CLK_TOP_AUD_ENGEN1_SEL 71 macro
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H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt8516-clk.h | 95 #define CLK_TOP_AUD_ENGEN1_SEL 71 macro
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H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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/u-boot/include/dt-bindings/clock/ |
H A D | mt8516-clk.h | 95 #define CLK_TOP_AUD_ENGEN1_SEL 71 macro
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H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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/u-boot/dts/upstream/include/dt-bindings/clock/ |
H A D | mt8516-clk.h | 178 #define CLK_TOP_AUD_ENGEN1_SEL 146 macro
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H A D | mt6765-clk.h | 149 #define CLK_TOP_AUD_ENGEN1_SEL 114 macro
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H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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H A D | mt8192-clk.h | 55 #define CLK_TOP_AUD_ENGEN1_SEL 43 macro
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt8516.c | 519 MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2), 705 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
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H A D | clk-mt8365.c | 448 MUX_GATE(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31),
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