Searched refs:CLK_TOP_AUD_2_SEL (Results 1 - 23 of 23) sorted by relevance
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 90 #define CLK_TOP_AUD_2_SEL 79 macro
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| H A D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 90 #define CLK_TOP_AUD_2_SEL 79 macro
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| H A D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 90 #define CLK_TOP_AUD_2_SEL 79 macro
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| H A D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 90 #define CLK_TOP_AUD_2_SEL 79 macro
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| H A D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 90 #define CLK_TOP_AUD_2_SEL 79 macro
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| H A D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 90 #define CLK_TOP_AUD_2_SEL 79 macro
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| H A D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 90 #define CLK_TOP_AUD_2_SEL 79 macro
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| H A D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8512-clk.h | 90 #define CLK_TOP_AUD_2_SEL 79 macro
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| H A D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 117 #define CLK_TOP_AUD_2_SEL 106 macro
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| H A D | mt8173-clk.h | 120 #define CLK_TOP_AUD_2_SEL 110 macro
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| H A D | mediatek,mt8365-clk.h | 89 #define CLK_TOP_AUD_2_SEL 79 macro
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| H A D | mt2712-clk.h | 157 #define CLK_TOP_AUD_2_SEL 126 macro
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| H A D | mt8192-clk.h | 60 #define CLK_TOP_AUD_2_SEL 48 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 447 MUX_GATE(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23),
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| H A D | clk-mt8512.c | 518 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents,
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